Rinse-removal of incubated nanotubes through selective exfoliation

US11271160B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11271160-B2
Application numberUS-202117320741-A
CountryUS
Kind codeB2
Filing dateMay 14, 2021
Priority dateNov 30, 2018
Publication dateMar 8, 2022
Grant dateMar 8, 2022

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  1. Title

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  5. First independent claim

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Abstract

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A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.

First claim

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The invention claimed is: 1. A method of forming a layer of carbon nanotubes on a substrate, the method comprising: depositing individual carbon nanotubes and at least one carbon nanotube aggregate on the substrate; forming an adhesive layer on the individual carbon nanotubes and the at least one carbon nanotube aggregate on the substrate, the adhesive layer adhering the individual carbon nanotubes to the substrate; and mechanically exfoliating the at least one carbon nanotube aggregate from the substrate. 2. The method of claim 1 , further comprising, before depositing the individual carbon nanotubes and the at least one carbon nanotube aggregate on the substrate: coating the substrate with a carbon nanotube adhesion promoter. 3. The method of claim 1 , wherein depositing the individual carbon nanotubes and the at least one carbon nanotube aggregate includes depositing via incubation, spin-coating, or dip coating. 4. The method of claim 1 , wherein depositing the individual carbon nanotubes and the at least one carbon nanotube aggregate includes incubating the substrate with a solution containing carbon nanotubes having a semiconducting carbon nanotube purity from about 99.9% to about 99.99%. 5. The method of claim 1 , wherein forming the adhesive layer includes forming a layer of a photoresist material on the individual carbon nanotubes. 6. The method of claim 5 , wherein the photoresist material is selected from the group consisting of polydimethyldiglutarimide (PMGI), hexamethyldisilazane (HMDS), and SPR. 7. The method of claim 1 , wherein forming the adhesive layer comprises: depositing a layer of polydimethyldiglutarimide (PMGI) on the individual carbon nanotubes and the at least one carbon nanotube aggregate on the substrate; and curing the layer of PMGI at a temperature of about 235° C. 8. The method of claim 7 , wherein the layer of PMGI has a thickness of from about 100 nm to about 150 nm. 9. The method of claim 1 , wherein mechanically exfoliating the at least one carbon nanotube aggregate from the substrate comprises: submerging the substrate in a solvent for a duration sufficient to remove a first portion of the adhesive layer and to retain a remaining portion of the adhesive layer; and sonicating the substrate in the solvent to remove the at least one carbon nanotube aggregate from the substrate, the remaining portion of the adhesive layer adhering the individual carbon nanotubes to the substrate during the sonicating. 10. The method of claim 9 , further comprising, while sonicating the substrate: filtering and/or circulating the solvent to remove carbon nanotube aggregates released from the substrate into the solvent. 11. The method of claim 9 , wherein the remaining portion of the adhesive layer is from about less than about 1 nm to about 2 nm in thickness. 12. The method of claim 1 , wherein mechanically exfoliating the at least one carbon nanotube aggregate from the substrate yields a substrate surface having fewer than ten carbon nanotube aggregates per square millimeter. 13. The method of claim 1 , wherein mechanically exfoliating the at least one carbon nanotube aggregate from the substrate yields a substrate surface having fewer than one carbon nanotube aggregate per square millimeter. 14. The method of claim 1 , wherein mechanically exfoliating the at least one carbon nanotube aggregate comprises mechanically exfoliating the at least one carbon nanotube aggregate without exfoliating the individual carbon nanotubes. 15. The method of claim 1 , further comprising: doping at least some of the individual carbon nanotubes to be n-channel carbon nanotubes. 16. The method of claim 1 , further comprising, prior to the depositing, coating the substrate with a carbon nanotube adhesion promoter to promote adhesion of the individual carbon nanotubes and the at least one carbon nanotube aggregate to the substrate. 17. A method of making a carbon nanotube logic device, the method comprising: depositing individual carbon nanotubes and carbon nanotube aggregates on a substrate; forming a polydimethyldiglutarimide (PMGI) layer on the substrate, the PMGI layer having a thickness of about 100 nm to about 150 nm; submerging the substrate in a solvent for a duration sufficient to remove a portion of the PMGI layer and to retain a remaining portion of the PMGI layer; and sonicating the substrate in the solvent to remove the carbon nanotube aggregates from the substrate to yield a substrate surface coated with individual carbon nanotubes and fewer than 10 carbon nanotube aggregates per square millimeter, the remaining portion of the adhesive layer adhering the individual carbon nanotubes to the substrate during the sonicating. 18. A method of making a carbon nanotube field effect transistor (CNFET) complementary metal-oxide semiconductor (CMOS) device, the method comprising: depositing a first channel of individual carbon nanotubes (CNTs) and a second channel of individual CNTs on the substrate, such that at least one carbon nanotube aggregate is also deposited on the substrate; forming an adhesive layer on the substrate, the adhesive layer adhering the first channel and the second channel to the substrate; mechanically exfoliating the at least one carbon nanotube aggregate from the substrate; forming, in electrical contact with the first channel, a first source electrode and a first drain electrode to generate a p-type metal-oxide semiconductor (PMOS) CNFET; and forming, in electrical contact with the second channel, a second source electrode and a second drain electrode to generate an n-type metal-oxide semiconductor (NMOS) CNFET. 19. The method of claim 18 , wherein the first source electrode and the first drain electrode are composed of platinum and the second source electrode and the second drain electrode are composed of titanium. 20. The method of claim 18 , further comprising: forming a layer of a nonstoichiometric oxide on the second channel via atomic layer deposition (ALD). 21. The method of claim 18 , further comprising, before depositing the first channel, the second channel, and the at least one carbon nanotube aggregate on the substrate: coating the substrate with a carbon nanotube adhesion promoter. 22. The method of claim 18 , wherein forming the adhesive layer includes forming a layer of a photoresist material on the first channel and the second channel. 23. The method of claim 18 , wherein mechanically exfoliating the at least one carbon nanotube aggregate from the substrate comprises: submerging the substrate in a solvent for a duration sufficient to remove a first portion of the adhesive layer and to retain a remaining portion of the adhesive layer; and sonicating the substrate in the solvent to remove the at least one carbon nanotube aggregate from the substrate, the remaining portion of the adhesive layer adhering the first channel and the second channel to the substrate during the sonicating.

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What does patent US11271160B2 cover?
A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the large…
Who is the assignee on this patent?
Massachusetts Inst Technology
What technology area does this patent fall under?
Primary CPC classification H01L51/0025. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).