Method for fabricating a finFET in a large scale integrated circuit

Patent metadata

Field	Value
Publication number	US-9136178-B2
Application number	US-201213877763-A
Country	US
Kind code	B2
Filing date	May 2, 2012
Priority date	Apr 9, 2012
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

Systems and methods of fabricating a FinFET in large scale integrated circuit are disclosed. One illustrative method relates to a dummy gate process, wherein the fin structure is only formed in the gate electrode region by performing a photolithography process and an etching of a first dummy gate on a flat STI surface using chemical mechanical polishing, forming drain and source regions, depositing a medium dielectric layer, polishing the medium dielectric layer till the top of the first dummy gate is exposed through the chemical mechanical polishing process again, removing the dummy gate material via a dry etching and a wet etching, and continuously etching the STI dielectric layer with the hard mask formed by the medium dielectric layer, thereafter performing the deposition of real gate dielectric and gate electrode material to complete the device structure.

First claim

The invention claimed is:

1. A method for fabricating a FinFET, comprising the following steps:
1) forming a STI isolation layer on a bulk silicon substrate, performing a well implantation and channel ion implantation to an active region and performing an annealing;
2) exposing a silicon surface of the active region, depositing a sacrificial gate oxide layer, forming a dummy gate on the sacrificial gate oxide layer, wherein the top of the dummy gate is covered by a composite har…

Assignees

• Li Ming
• Huang Ru
• Univ Beijing

Inventors

• Li Ming
• Huang Ru

Classifications

• H10P30/222

  Electricity · mapped topic

• H10P30/212

  Electricity · mapped topic

• H10P30/208

  Electricity · mapped topic

• H10P30/204

  Electricity · mapped topic

• H10D64/01326 Primary

  Electricity · mapped topic