Wafer handling chamber with moisture reduction

Patent metadata

Field	Value
Publication number	US-11270899-B2
Application number	US-201916423824-A
Country	US
Kind code	B2
Filing date	May 28, 2019
Priority date	Jun 4, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

An apparatus and method for reducing moisture within a wafer handling chamber is disclosed. The moisture reduction results in reduced oxidation of a wafer. The moisture reduction is made possible through use of valves and purging gas. Operation of the valves may result in improved localized purging.

First claim

What is claimed is:

1. A wafer handling chamber configured for handling a semiconductor substrate, the chamber comprising:
a housing;
a first gate valve disposed on the housing, wherein the first gate valve is configured to allow a semiconductor substrate to pass and enter into the housing;
a first injector port disposed proximate the first gate valve; a first isolation valve disposed outside the housing;
a first flow restrictor coupled to the first isolation valve, wherein the first isolation valve and the first flow restrictor adjust an amount of a purge gas flowing to the first injector port;
a loadlock injector port disposed within the housing;
a loadlock isolation valve disposed outside the housing;
a loadlock flow restrictor coupled to the loadlock isolation valve, wherein the loadlock isolation valve and the loadlock flow restrictor adjust an amount of the purge gas flowing to the loadlock injector port; and
a flow controller configured to adjust an amount of purge gas flowing to the housing;
wherein closing the first isolation valve results in a reduced amount of the purge gas flowing to the first injector port;
wherein closing the loadlock isolation valve results in a reduced amount of the purge gas flowing to the loadlock injector port; and
wherein flowing the purge gas through the first injector port results in a lower oxygen content in the film on the semiconductor substrate.

2. The chamber of claim 1 , wherein the purge gas comprises at least one of:
nitrogen (N 2 ); argon (Ar); hydrogen (H 2 ); and krypton (Kr).

3. The chamber of claim 1 , further comprising:
a second gate valve disposed on the housing, wherein the second gate valve is configured to allow a semiconductor substrate to pass and enter into the housing;
a second injector port disposed near the second gate valve; a second isolation valve disposed outside the housing; and
a second flow restrictor coupled to the second isolation valve, wherein the second isolation valve and the second flow restrictor adjust an amount of a purge gas flowing to the second injector port.

4. The chamber of claim 3 , further comprising:
a third gate valve disposed on the housing, wherein the third gate valve is configured to allow a semiconductor substrate to pass and enter into the housing;
a third injector port disposed near the third gate valve;
a third isolation valve disposed outside the housing; and
a third flow restrictor coupled to the third isolation valve, wherein the third isolation valve and the third flow restrictor adjust an amount of a purge gas flowing to the third injector port.

5. The chamber of claim 4 , further comprising:
a fourth gate valve disposed on the housing, wherein the fourth gate valve is configured to allow a semiconductor substrate to pass and enter into the housing;
a fourth injector port disposed near the fourth gate valve; a fourth isolation valve disposed outside the housing; and
a fourth flow restrictor coupled to the fourth isolation valve, wherein the fourth isolation valve and the fourth flow restrictor adjust an amount of a purge gas flowing to the fourth injector port.

6. The chamber of claim 5 , wherein closing each of the first isolation valve and the first gate valve, the second isolation valve and the second gate valve, the third isolation valve and the third gate valve, the fourth isolation valve and the fourth gate valve, and the loadlock isolation valve results in an even distribution of gas to the first injector port, the second injector port, the third injector port, the fourth injector port, and the loadlock injector port.

7. The chamber of claim 5 , wherein opening only the first isolation valve and the first gate valve results in an increased localized purging at the first injector port.

8. The chamber of claim 5 , further comprising a ring of injector ports disposed within the housing.

9. The chamber of claim 8 , wherein the ring of injector ports are selectively operated to allow purging at a particular injector port to be turned on and off.

10. The chamber of claim 1 , wherein the flow controller comprises at least one of:
a mass flow controller or a pressure flow controller.

11. A reaction system configured for depositing a film on a semiconductor substrate, the system comprising:
a first reaction chamber configured to flow at least one gas onto a semiconductor substrate to form a film on the semiconductor substrate; and
a wafer handling chamber coupled to the first reaction chamber, the wafer handling chamber comprising:
a housing;
a first gate valve disposed on the housing, wherein the first gate valve is configured to allow a semiconductor substrate to travel between the first reaction chamber and the wafer handling chamber;
a first injector port disposed proximate the first gate valve; a first isolation valve disposed outside the housing;
a first flow restrictor coupled to the first isolation valve, wherein the first isolation valve and the first flow restrictor adjust an amount of a purge gas flowing to the first injector port;
a loadlock injector port disposed within the housing;
a loadlock isolation valve disposed outside the housing;
a loadlock flow restrictor coupled to the loadlock isolation valve, wherein the loadlock isolation valve and the loadlock flow restrictor adjust an amount of the purge gas flowing to the loadlock injector port; and
a flow controller configured to adjust an amount of purge gas flowing to the housing;
wherein closing the first isolation valve results in a reduced amount of the purge gas flowing to the first injector port; and
wherein closing the loadlock isolation valve results in a reduced amount of the purge gas flowing to the loadlock injector port;

wherein the flow of the purge gas occurs at the first injector port when the first gatevalve is open and the semiconductor substrate travels between the first reaction chamber and the wafer handling chamber; and
wherein flowing the purge gas through the first injector port results in a lower oxygen content in the film on the semiconductor substrate.

12. The reaction system of claim 11 , further comprising: a second reaction chamber configured to flow at least one gas onto a semiconductor substrate to etch a film on the semiconductor substrate.

13. The reaction system of claim 11 , wherein the purge gas comprises at least one of: nitrogen (N 2 ); argon (Ar); hydrogen (H 2 ); and krypton (Kr).

14. The reaction system of claim 11 , wherein the flow controller comprises at least one of: a mass flow controller or a pressure flow controller.

15. A wafer handling chamber configured for handling a semiconductor substrate, the chamber comprising:
a housing;
a first gate valve disposed on the housing, wherein the first gate valve is configured to allow a semiconductor substrate to pass and enter into the housing;
a first injector port disposed proximate the first gate valve;
a first isolation valve disposed outside the housing;
a first flow restrictor coupled to the first isolation valve, wherein the first isolation valve and the first flow restrictor adjust an amount of a purge gas flowing to the first injector port;
a second gate valve disposed on the housing, wherein the second gate valve is configured to allow a semiconductor substrate to pass and enter into the housing;
a second injector port disposed near the second gate valve; a second isolation valve disposed outside thehousing;
a second flow restrictor coupled to the second isolation valve, wherein the second isolation valve and the second flow restrictor adjust an amount of a purge gas flowing to the second in

Assignees

• Asm Ip Holding Bv

Inventors

• Raisanen Petri
• Johnson Ward

Classifications

• H10P72/0466

  characterised by the construction of the load-lock chamber · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P72/1926 Primary

  characterised by the presence of atmosphere modifying elements inside or attached to the closed carrier · CPC title

• H10P72/0464

  characterised by the construction of the transfer chamber · CPC title

• H10P72/0402 Primary

  Apparatus for fluid treatment (H10P72/0441, H10P72/0448 take precedence) · CPC title