Methods for removal of selected nanowires in stacked gate all around architecture

Patent metadata

Field	Value
Publication number	US-10056254-B2
Application number	US-201715467279-A
Country	US
Kind code	B2
Filing date	Mar 23, 2017
Priority date	Oct 12, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first thickness and a layer of SiGe having a second thickness. The second set of fins includes a second stack of layer pairs where at least one layer pair contains a layer of Si having the first thickness and a layer of SiGe having a third thickness greater than the second thickness. The method further includes removing the layers of SiGe from the first stack leaving first stacked Si nanowires spaced apart by a first distance and from the second stack leaving second stacked Si nanowires spaced apart by a second distance corresponding to the third thickness. The method further includes forming a first dielectric layer on the first nanowires and a second, thicker dielectric layer on the second nanowires.

First claim

What is claimed is:

1. A method, comprising:
forming over a common substrate a first set of fins and a second set of fins both having a same total thickness, the first set of fins comprising a first stack comprised of a plurality of layer pairs where each layer pair is comprised of a layer of Si having a first thickness and a layer of SiGe having a second thickness, the second set of fins comprising a second stack comprised of a plurality of layer pairs where at least one layer pair is comprised of a layer of Si having the first thickness and a layer of SiGe having a third thickness, where the second thickness is less than the third thickness;
removing the layers of SiGe from the first stack leaving a first plurality of vertically stacked first Si nanowires that are spaced apart by a first distance corresponding to the second thickness;
removing the layers of SiGe from the second stack leaving a second plurality of vertically stacked second Si nanowires that are spaced apart by a second distance corresponding to the third thickness, where there are fewer vertically stacked second Si nanowires than vertically stacked first Si nanowires; and
forming a first oxide layer and a metal layer on each of the first Si nanowires and a second oxide layer and a metal layer on each of the second Si nanowires, where the second oxide layer on the second Si nanowires is thicker than the first oxide layer on the first Si nanowires.

2. The method as in claim 1 , where the first oxide layer is comprised of a layer of high dielectric constant metal oxide and where the second oxide layer is comprised of a layer of silicon oxide having an overlying layer of high dielectric constant metal oxide.

3. The method as in claim 1 , where the SiGe layers are comprised of Si 1-x Ge x , where x is in a range of about 0.1 to about 0.35.

4. The method as in claim 1 , where forming the first set of fins and the second set of fins comprises:
depositing a first plurality of layer pairs on the substrate, where each layer pair of the first plurality is comprised of the layer of Si having the first thickness and the layer of SiGe having the second thickness;
removing in a region of the substrate the deposited first plurality of layer pairs;
depositing in the region a second plurality of layer pairs on the substrate, where at least one layer pair of the second plurality is comprised of layer of Si having the first thickness and the layer of SiGe having a third thickness; and
defining the first set of fins in the deposited first plurality of layer pairs and defining the second set of fins in the deposited second plurality of layer pairs.

5. The method as in claim 1 , where forming the first set of fins and the second set of fins comprises:
depositing a plurality of layer pairs on the substrate, where each layer pair of the plurality of layer pairs is comprised of the layer of Si having the first thickness and the layer of SiGe having the second thickness;
in a portion of the deposited plurality of layer pairs, implanting Ge into at least one of the layers of Si so as to convert the implanted Si layer into a layer comprised of SiGe that is interposed between two adjacent layers of SiGe to form a thicker layer of SiGe having the third thickness; and
defining the first set of fins in the deposited plurality of layer pairs and defining the second set of fins in the implanted portion of the deposited layer pairs.

6. The method as in claim 5 , further comprising performing one of a solid-phase epitaxy or a solid-phase crystallization (SPE/SPC) operation at a predetermined temperature to heal implant-induced damage.

7. The method as in claim 6 , where the predetermined temperature is less than about 700° C.

8. The method as in claim 1 , where forming the first set of fins and the second set of fins comprises
depositing a plurality of layer pairs on the substrate, where each layer pair is comprised of the layer of Si having the first thickness and the layer of SiGe having the second thickness, and where depositing the plurality of layer pairs also deposits a first layer of Ge adjacent to a first surface of a layer of Si of at least one layer pair and a second layer of Ge adjacent to a second opposite surface of the layer of Si, where the layer of Si and the first and, second layers of Ge are interposed between a first layer of SiGe and a second layer of SiGe, each layer of Ge having a fourth thickness that is less than the first and second thicknesses;
forming the first set of fins in a first region of the deposited plurality of layers and the second set of fins a second region in a second region of the deposited plurality of layers;
in the first set of fins, removing the layers of SiGe and the layers of Ge leaving the first plurality of vertically stacked first Si nanowires that are spaced apart by a first distance that is substantially equal to the second thickness plus the fourth thickness;
in the second set of fins, performing an anneal at a predetermined temperature to intermix the layers of Ge with the layer of Si that is interposed between the layers of Ge, and the layers of SiGe, to form a layer of SiGe having the third thickness; and
in the second region, removing the layers of SiGe leaving the second plurality of vertically stacked second Si nanowires that are spaced apart by the second distance that is substantially equal to the third thickness plus the fourth thickness.

9. The method as in claim 8 , where the predetermined temperature is about 800° C.

10. The method as in claim 1 , where the first thickness is about 8 nm to about 10 nm, where the second thickness is about 8 nm to about 10 nm, and where the third thickness is about three times the first thickness.

11. The method as in claim 1 , where the first thickness is about 8 nm to about 10 nm, where the second thickness is about 8 nm to about 10 nm, where the third thickness is about three times the first thickness, and where the fourth thickness is about 2 nm to about 3 nm.

12. The method as in claim 1 , where the plurality of vertically stacked first Si nanowires are processed so as to comprise part of a channel of a first finFET used in a first type of circuit, and where the plurality of vertically stacked second Si nanowires are processed so as to comprise part of a channel of a second finFET used in a second type of circuit.

13. The method of claim 12 , where the first type of circuit comprises logic or memory, and where the second type of circuit comprises input/output or analog.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3462 Primary

  Nanowires · CPC title