Cache optimization for graphics systems

Patent metadata

Field	Value
Publication number	US-10482028-B2
Application number	US-201715493757-A
Country	US
Kind code	B2
Filing date	Apr 21, 2017
Priority date	Apr 21, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

First claim

What is claimed is:

1. An apparatus comprising:
one or more processors including a graphics processor, the one or more processors to:
determine a type of each of one or more caches associated with the one or more processors;
introduce cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits are to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches;
upon detecting an invalidation for the one or more caches, implement and increment the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss; and
facilitate replacement or re-allocation of locations of old cache coloring bits.

2. The apparatus of claim 1 , wherein the one or more processors to detect the type of the one or more caches including the one or more processors to detect read-only caches and read/write caches.

3. The apparatus of claim 2 , wherein for a detected cache that is a read-only cache, the one or more processors are further to track the old cache coloring bits to ensure related entries are reallocated before the old cache coloring bits are regarded as reusable.

4. The apparatus of claim 2 , wherein for a detected cache that is a read/write cache, the one or more processors are further to track locations of old cache coloring bits and regard the locations as a miss.

5. The apparatus of claim 1 , wherein the one or more processors are to define the cache coloring bits and associate the defined cache coloring bits with the one or more caches as part of a tag.

6. The apparatus of claim 1 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

7. A method comprising:
detecting a type of each of one or more caches associated with one or more processors including a graphics processor;
introducing cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits are to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches;
upon detecting an invalidation for the one or more caches, implementing and incrementing the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss; and
facilitating replacement or re-allocation of locations of old cache coloring bits.

8. The method of claim 7 , wherein detecting the type of each of the one or more caches including detecting read-only caches and read/write caches.

9. The method of claim 8 , further comprising:
for a detected cache that is a read-only cache, further comprising tracking the old cache coloring bits to ensure related entries are reallocated before the old cache coloring bits are regarded as reusable.

10. The method of claim 8 , further comprising:
for a detected cache that is a read/write cache, further comprising tracking locations of old cache coloring bits and regarding the locations as a miss.

11. The method of claim 7 , further comprising defining the cache coloring bits and associating the defined cache coloring bits with the one or more caches as part of a tag.

12. The method of claim 7 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

13. At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
detecting one or more caches associated with one or more processors including a graphics processor;
introducing cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches;
upon detecting an invalidation for the one or more caches, implementing and incrementing the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss; and
facilitating replacement or re-allocation of locations of old cache coloring bits.

14. The machine-readable medium of claim 13 , wherein detecting the type of each of the one or more caches including detecting read-only caches and read/write caches.

15. The machine-readable medium of claim 14 , further comprising instructions that, when executed by the computing device, cause the computing device to perform operations comprising:
for a detected cache that is a read-only cache, tracking the old cache coloring bits to ensure related entries are reallocated before the old cache coloring bits are regarded as reusable.

16. The machine-readable medium of claim 14 , further comprising instructions that, when executed by the computing device, cause the computing device to perform operations comprising:
for a detected cache that is a read/write cache, tracking locations of old cache coloring bits and regarding the locations as a miss.

17. The machine-readable medium of claim 13 , further comprising instructions that, when executed by the computing device, cause the computing device to perform operations comprising:
defining the cache coloring bits and associating the defined cache coloring bits with the one or more caches as part of a tag.

18. The machine-readable medium of claim 13 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Vembu Balaji
• Ray Joydeep
• Appu Abhishek R

Classifications

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F2212/1048

  Scalability · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title