Stacked semiconductor package having mold vias and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11257801-B2
Application number	US-201916528938-A
Country	US
Kind code	B2
Filing date	Aug 1, 2019
Priority date	May 11, 2017
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

First claim

What is claimed is:

1. A method for manufacturing a stacked semiconductor package, comprising:
disposing first semiconductor chips having first active surfaces over which first bonding pads including peripheral bonding pads and a central bonding pad are arranged, over a carrier wafer such that the carrier wafer and the first active surfaces face each other;
forming a first encapsulation member which covers the first semiconductor chips, over the carrier wafer such that a reconfigured wafer in which the first semiconductor chips are redisposed is constructed;
removing the carrier wafer from the reconfigured wafer;
bonding two second semiconductor chips to one first semiconductor chip on the reconfigured wafer at a distance from each other, wherein the second semiconductor chips have second active surfaces over which second bonding pads are arranged at side peripheries adjacent to the first semiconductor chip, wherein the second semiconductor chips have first coupling members formed on the second bonding pads, wherein the second semiconductor chips possess a thickness greater than a target thickness, and wherein the second semiconductor chips are disposed on the reconfigured wafer, such that the second active surfaces face the first active surface, the second bonding pads are coupled with the peripheral bonding pads by the first coupling members and the central bonding pad is exposed;
forming a second encapsulation member over the reconfigured wafer in such a way as to cover the second semiconductor chips;
removing a partial thickness of the second encapsulation member and the second semiconductor chips such that the target thickness of the second semiconductor chips remains; and
forming a mold via which is coupled with the central bonding pad of the first semiconductor chip, and which pass through a portion of the second encapsulation member in a region between the second semiconductor chips,
after the forming of the mold via:
forming a bump pad which is disposed over the mold via and dummy pads which are disposed over second surfaces of the second semiconductor chips; and
forming a second coupling member over the bump pad, and forming support members over the dummy pads;
wherein the first semiconductor chip and the mold via do not include any through via for connecting between the peripheral bonding pads and the second bonding pads.

2. The method according to claim 1 further comprising, after the forming of the second coupling member and the support members:
sawing a resultant product with the second coupling member and the support members such that the resultant product is separated into a plurality of chip stacks including the first and second semiconductor chips, the first and second encapsulation members and the mold via.

3. The method according to claim 2 , further comprising, after the sawing of the resultant product:
bonding the chip stacks to a top surface of a substrate having the top surface over which a bond finger is arranged and a bottom surface under which an electrode terminal is arranged, such that the second coupling member and the bond finger are coupled with each other;
forming a third encapsulation member over the substrate in such a way as to cover side surfaces of the first and second encapsulation members;
partially removing the third encapsulation member and the first back surface of the first encapsulation member such that the first surfaces of the first semiconductor chips are exposed; and
forming an external coupling member over the electrode terminal.

4. The method according to claim 3 , further comprising, after the forming of the external coupling members:
singulating a resultant product such that the resultant product is separated into individual packages.

5. The method according to claim 2 , further comprising, after the sawing of the resultant product:
bonding a chip stack to a top surface of a substrate having the top surface over which a bond finger is arranged and a bottom surface under which an electrode terminal is arranged, such that the second coupling member and the bond finger are coupled with each other;
forming an underfill to fill spaces between the second semiconductor chips and the second encapsulation member and the top surface of the substrate; and
forming an external coupling member over the electrode terminal.

6. The method according to claim 5 , further comprising, after the forming of the external coupling members:
singulating a resultant product such that the resultant product is separated into individual packages.

7. The method according to claim 2 , further comprising, after the forming of the mold vias:
forming a first dielectric layer under second surfaces of the second semiconductor chips facing away from the second active surfaces, and the second encapsulation member in such a way as to leave exposed the mold via;
forming, under the first dielectric layer, a redistribution line having one end which is coupled with the exposed mold via;
forming a second dielectric layer under the redistribution line and the first dielectric layer in such a way as to expose the other end of the redistribution line facing away from the one end; and
forming, under the second dielectric layer, a redistribution pad which is coupled with the exposed other end of the redistribution line.

8. The method according to claim 7 , further comprising, after the forming of the redistribution pad:
forming an external coupling member under the redistribution pad; and
singulating a resultant product such that the resultant product is separated into individual packages.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sang-Eun
• Lee Hyung-Dong
• Ko Eun

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/853

  On the same surface · CPC title

• H10W72/9413

  on encapsulations · CPC title