Interposer for a package-on-package structure

Patent metadata

Field	Value
Publication number	US-2016358899-A1
Application number	US-201514733201-A
Country	US
Kind code	A1
Filing date	Jun 8, 2015
Priority date	Jun 8, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

First claim

1 . A package-on-package (PoP) structure comprising:
a first die; a second die; and a memory device configured to electrically couple to the first die and to the second die by an interposer between the first die and the second die, the interposer comprising copper-filled vias within a mold.

2 . The POP structure of claim 1 , wherein the mold comprises a photo-dielectric mold.

3 . The POP structure of claim 1 , wherein the interposer is configured to:
route first electrical signals between the memory device and the first die; and route second electrical signals between the memory device and the second die.

4 . The PoP structure of claim 3 , further comprising a bottom interposer configured to electrically couple to the interposer, wherein the first electrical signals are routed between the memory device and the first die by way of the bottom interposer, and wherein the second electrical signals are routed between the memory device and the second die by way of the bottom interposer.

5 . The PoP structure of claim 1 , wherein the memory device includes a wide input/output (I/O) memory device.

6 . The PoP structure of claim 5 , wherein the wide I/O memory device includes between approximately 1700 I/O ports and 2000 I/O ports.

7 . The PoP structure of claim 1 , wherein the memory device is included in a first package of the PoP structure.

8 . The PoP structure of claim 1 , wherein the first die, the second die, and the interposer are included in a second package of the PoP structure.

9 . The PoP structure of claim 1 , wherein the first die, the second die, the memory device, and the interposer are integrated into a wireless device, a communications device, a personal digital assistant (PDA), a navigation device, a music player, a video player, an entertainment unit, a fixed location data unit, and a computer.

10 . A method for forming a package-on-package (PoP) structure, the method comprising:
coupling a first die and a second die to a bottom interposer; forming a mold on the first die, the second die, and the bottom interposer; etching one or more vias within the mold, the one or more vias located between the first die and the second die; depositing a barrier/seed deposition layer into the one or more vias prior to filling the one or more vias with copper; and filling the one or more vias with copper to form an interposer having one or more copper-filled vias.

11 . The method of claim 10 , wherein the mold comprises a photo-dielectric mold.

12 . The method of claim 10 , wherein the one or more copper-filled vias are electrically coupled to the bottom interposer, and wherein the bottom interposer is electrically coupled to the first die and to the second die.

13 . The method of claim 10 , further comprising coupling a memory device to the first die, the second die, and the interposer, the interposer configured to route electrical signals between the memory device and at least one of the first die or the second die.

14 . The method of claim 13 , wherein the PoP structure comprises the interposer, the first die, the second die, the bottom interposer, and the memory device.

15 . The method of claim 13 , wherein the memory device includes a wide input/output (I/O) memory device.

16 . The method of claim 15 , wherein the wide I/O memory device includes between approximately 1700 I/O ports and 2000 I/O ports.

17 . The method of claim 13 , wherein the memory device is included in a first package of the PoP structure, and wherein the first die, the second die, and the interposer are included in a second package of the PoP structure.

18 . (canceled)

19 . The method of claim 10 , wherein coupling the first die and the second die onto the bottom interposer is performed using fabrication equipment, wherein forming the mold is performed using the fabrication equipment, wherein etching the one or more vias is performed using the fabrication equipment, and wherein filling the one or more vias with the copper is performed using the fabrication equipment.

20 . A non-transitory computer-readable medium comprising data for forming a package-on-package (PoP) structure, the data, when used by fabrication equipment, causes the fabrication equipment to:
couple a first die and a second die onto a bottom interposer; form a mold on the first die, the second die, and the bottom interposer; etch one or more vias within the mold, the one or more vias located between the first die and the second die; deposit a barrier/seed deposition layer into the one or more vias prior to filling the one or more vias with copper; and fill the one or more vias with copper to form an interposer having one or more copper-filled vias.

21 . The non-transitory computer-readable medium of claim 20 , wherein the mold comprises a photo-dielectric mold.

22 . The non-transitory computer-readable medium of claim 20 , wherein the one or more copper-filled vias are electrically coupled to the bottom interposer, and wherein the bottom interposer is electrically coupled to the first die and to the second die.

23 . The non-transitory computer-readable medium of claim 20 , wherein the data further causes the fabrication equipment to couple a memory device to the first die, the second die, and the interposer, the interposer configured to route electrical signals between the memory device an at least one of the first die or the second die.

24 . The non-transitory computer-readable medium of claim 23 , wherein the PoP structure comprises the interposer, the first die, the second die, the bottom interposer, and the memory device.

25 . The non-transitory computer-readable medium of claim 23 , wherein the memory device includes a wide input/output (I/O) memory device.

26 . The non-transitory computer-readable medium of claim 25 , wherein the wide I/O memory device includes between approximately 1700 I/O ports and 2000 I/O ports.

27 . The non-transitory computer-readable medium of claim 23 , wherein the memory device is included in a first package of the PoP structure, and wherein the first die, the second die, and the interposer are included in a second package of the PoP structure.

28 . (canceled)

29 . A package-on-package (PoP) structure comprising:
means for performing a first logical function; means for performing a second logical function; means for storing data, the means for storing data configured to electrically couple to the means for performing the first logical function and configured to electrically couple to the means for performing the second logical function; and means for routing electrical signals between the means for storing data and at least one of the means for performing the first logical function or the means for performing the second logical function, the means for routing electrical signals is between the means for performing the first logical function and the means for performing the second logical function, and the means for routing electrical signals comprising copper-filled vias formed within a mold.

30 . The POP structure of claim 29 , wherein the mold comprises a photo-dielectric mold.

Assignees

• Qualcomm Inc

Inventors

• Lee Jae Sik
• Hwang Kyu-Pyung
• We Hong Bok

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title