Half density ferroelectric memory and operation

Patent metadata

Field	Value
Publication number	US-11250900-B2
Application number	US-202017001296-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Jun 13, 2016
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

First claim

What is claimed is:

1. A method, comprising:
selecting a first memory cell and a second memory cell;
activating a sense component coupled with the first memory cell and the second memory cell based at least in part selecting the first memory cell and the second memory cell;
selecting a third memory cell and a fourth memory cell;
activating a switch to couple the third memory cell with the sense component based at least in part on selecting the third memory cell and the fourth memory cell; and
determining a logic state of the third memory cell based at least in part on a logic state of the fourth memory cell.

2. The method of claim 1 , further comprising:
determining a logic state of the fourth memory cell based at least in part on selecting the third memory cell and the fourth memory cell.

3. The method of claim 1 , wherein determining the logic state of the third memory cell comprises:
comparing the logic state of the third memory cell to the logic state of the fourth memory cell at the sense component.

4. The method of claim 1 , further comprising:
determining a logic state of the first memory cell based at least in part on a logic state of the second memory cell.

5. The method of claim 1 , further comprising:
activating a second switch to couple the first memory cell with the sense component, wherein activating the sense component is based at least in part on activating the second switch.

6. The method of claim 1 , further comprising:
deactivating a second sense component coupled with the second memory cell based at least in part on activating the sense component.

7. The method of claim 1 , further comprising:
applying a threshold voltage to a transistor of the switch to couple the fourth memory cell with the sense component.

8. The method of claim 1 , further comprising:
applying a voltage to an isolation component to couple the third memory cell with the sense component.

9. The method of claim 1 , wherein the fourth memory cell is configured to provide a reference input to the sense component for sensing the third memory cell.

10. The method of claim 1 , wherein the second memory cell is configured to provide a reference input to the sense component for sensing the first memory cell.

11. An electronic memory apparatus, comprising:
a first memory cell;
a second memory cell coupled with the first memory cell;
a sense component coupled with the first memory cell and the second memory cell;
a third memory cell coupled with the sense component;
a fourth memory cell coupled with the sense component; and
a controller coupled with the sense component, the first memory cell and second memory cells, or the third memory cell and the fourth memory cell, wherein the controller is operable to:
select the first memory cell and the second memory cell;
activate the sense component based at least in part selecting the first memory cell and the second memory cell;
select the third memory cell and the fourth memory cell;
activate a switch to couple the third memory cell with the sense component based at least in part on selecting the third memory cell and the fourth memory cell; and
determine a logic state of the third memory cell based at least in part on a logic state of the fourth memory cell.

12. The electronic memory apparatus of claim 11 , wherein the controller is operable to:
determine a logic state of the first memory cell based at least in part on a logic state of the second memory cell.

13. The electronic memory apparatus of claim 11 , wherein the controller is operable to:
determine a logic state of the fourth memory cell based at least in part on selecting the fourth memory cell.

14. The electronic memory apparatus of claim 11 , wherein the controller is operable to:
compare the logic state of the third memory cell to the logic state of the fourth memory cell.

15. The electronic memory apparatus of claim 11 , wherein the controller is operable to:
apply a threshold voltage to the switch; and
couple the fourth memory cell with the sense component based at least in part on applying the threshold voltage to the switch.

Assignees

• Micron Technology Inc

Inventors

• Derner Scott J
• Ingalls Charles L

Classifications

• G11C2211/5634

  Reference cells · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title