Dual mode memory array security apparatus, systems and methods

Patent metadata

Field	Value
Publication number	US-10068631-B2
Application number	US-201514794560-A
Country	US
Kind code	B2
Filing date	Jul 8, 2015
Priority date	Jul 8, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

First claim

What is claimed is:

1. A physically unclonable function (“PUF”) pattern generator, comprising:
a dual-mode ferroelectric random access memory (“FRAM”) array capable of storing an imprinted read-only (“RO”) data bit and a non-imprinted read/write (“R/W”) data bit per array storage cell, cells of the FRAM array being imprinted with a PUF pattern, the FRAM array including a plurality of dual mode FRAM storage cells, each of the FRAM storage cells including two half-cells; and
PUF read logic communicatively coupled to the dual mode FRAM array to receive a PUF read command and to sequence RO mode access commands to the FRAM array in order to sense states of the cells of the FRAM array and to generate an as-read PUF pattern.

2. The PUF pattern generator of claim 1 , further comprising:
cryptographic key generation logic coupled to the dual mode FRAM array to receive the as-read PUF pattern and to generate a cryptographic key from the as-read PUF pattern in response to a CRYPTO KEYGEN command.

3. The PUF pattern generator of claim 1 , further comprising:
authentication logic coupled to the PUF read logic to receive an authentication request for RO mode access, to authenticate the RO mode access request, and to pass the PUF read command to the PUF read logic following authentication.

4. The PUF pattern generator of claim 1 , further comprising:
error-correcting code (“ECC”) logic coupled to the dual mode FRAM array to perform error detection and correction operations on the as-read PUF pattern.

5. The PUF pattern generator of claim 1 , wherein the dual mode FRAM storage cells are dual mode 2T/2C FRAM storage cells, the FRAM array further comprising:
a switching matrix coupled to each FRAM storage cell to switch a bit line associated with each half-cell for write access to the FRAM storage cell and read access from the FRAM storage cell; and
dual mode state control logic coupled to the switching matrix and to the PUF read logic to control switches associated with the switching matrix to enable full-cell read access and both full-cell and half-cell write access by sequencing the switches according to a first sequence to perform read operations of read/write (“R/W”) data and by sequencing the switches according to a second sequence to perform read operations of the imprinted RO data.

Assignees

• Texas Instruments Inc

Inventors

• Juvekar Chiraag
• Kwong Joyce
• Bittlestone Clive
• Ramaswamy Srinath

Classifications

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G11C11/2295 Primary

  Protection circuits or methods · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title