Power reduction for a sensing operation of a memory cell

Patent metadata

Field	Value
Publication number	US-9715918-B1
Application number	US-201615161952-A
Country	US
Kind code	B1
Filing date	May 23, 2016
Priority date	May 23, 2016
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. For example, a first and second set of memory cells with a common word like may be selected for a read operation. A first set of sensing components corresponding to the first set of memory cells may be activated for the read operation, and a second set of sensing components that correspond to the second set of memory cells may be maintained in a deactivated state.

First claim

What is claimed is:

1. A method of operating a ferroelectric memory array, comprising:
selecting a first set of memory cells and a second set of memory cells for a read operation using a word line that is in electronic communication with the first set of memory cells and the second set of memory cells, wherein each memory cell of the first set of memory cells and each memory cell of the second set of memory cells comprises a ferroelectric capacitor;
activating a first set of sensing components corresponding to the first set of memory cells for the read operation; and
maintaining a second set of sensing components that correspond to the second set of memory cells in a deactivated state during the read operation.

2. The method of claim 1 , further comprising:
shorting a digit line for each memory cell of the second set of memory cells with a plate line during the read operation, wherein the plate line is in electronic communication with the first set of memory cells and the second set of memory cells.

3. The method of claim 2 , wherein the digit line for each memory cell of the second set of memory cells is in electronic communication with the plate line via a switching component, and wherein shorting the digit line comprises:
activating the switching component during the read operation.

4. The method of claim 2 , wherein a voltage of the plate line is a fixed voltage.

5. The method of claim 1 , further comprising:
isolating a digit line for each memory cell of the first set of memory cells from a plate line during the read operation.

6. The method of claim 5 , wherein the digit line for each memory cell of the first set of memory cells is in electronic communication with the plate line via a switching component, and wherein isolating the digit line for each memory cell comprises:
deactivating the switching component during the read operation.

7. The method of claim 1 , wherein the word line is in electronic communication with a third set of memory cells and a fourth set of memory cells, and wherein the method further comprises:
selecting the third set of memory cells and the fourth set of memory cells using the word line.

8. The method of claim 7 , wherein a third set of sensing components is in electronic communication with the third set of memory cells and a fourth set of sensing components is in electronic communication with the fourth set of memory cells, and wherein the method further comprises:
activating the third set of sensing components for the read operation.

9. The method of claim 8 , further comprising:
maintaining the fourth set of sensing components in the deactivated state during the read operation based at least in part on activating the third set of memory cells.

10. The method of claim 1 , wherein the first set of sensing components and the second set of sensing components are arranged in an interleaved pattern that comprises a first sensing component of the first set of sensing components adjacent to a first sensing component and a second sensing component of the second set of sensing components.

11. An electronic memory apparatus, comprising:
a first set of memory cells corresponding to a first set of sensing components,
a second set of memory cells corresponding to a second set of sensing components, wherein each memory cell of the first set of memory cells and the second set of memory cells comprises a ferroelectric capacitor;
a word line in electronic communication with the first set of memory cells and the second set of memory cells; and
a controller in electronic communication with the first set of sensing components and the second set of sensing components, wherein the controller is operable to activate the first set of sensing components and the second set of sensing components independently of one another.

12. The electronic memory apparatus of claim 11 , wherein the controller comprises:
a first driver that is in electronic communication with the first set of sensing components; and
a second driver that is in electronic communication with the second set of sensing components.

13. The electronic memory apparatus of claim 11 , wherein each sensing component of the first set of sensing components is in electronic communication with the controller via a first control line, and wherein each sensing component of the second set of sensing components is in electronic communication with the controller via a second control line.

14. The electronic memory apparatus of claim 11 , wherein the first set of sensing components and the second set of sensing components are arranged in an interleaved pattern that comprises a first sensing component of the first set of sensing components adjacent to a first sensing component and a second sensing component of the second set of sensing components.

15. The electronic memory apparatus of claim 11 , further comprising:
a plate line in electronic communication with the first set of memory cells and the second set of memory cells.

16. The electronic memory apparatus of claim 15 , further comprising:
a first set of switching components in electronic communication with a digit line associated with each memory cell of the first set of memory cells and the plate line; and
a second set of switching components in electronic communication with a digit line associated with each memory cell of the second set of memory cells and the plate line.

17. The electronic memory apparatus of claim 16 , wherein each switching component of the first set of switching components is in electronic communication with the controller via a first control line, and wherein each switching component of the second set of switching components is in electronic communication with the controller via a second control line.

18. The electronic memory apparatus of claim 11 , wherein each sensing component of the first set of sensing components is in electronic communication with a respective memory cell of the first set of memory cells and each sensing component of the second set of sensing components is in electronic communication with a respective memory cell of the second set of memory cells.

19. The electronic memory apparatus of claim 11 , further comprising:
a third set of memory cells corresponding to a third set of sensing components,
a fourth set of memory cells corresponding to a fourth set of sensing components; wherein:
the word line is in electronic communication with the third set of memory cells and the fourth set of memory cells,
the controller is in electronic communication with the third set of sensing components and the fourth set of sensing components, and
the controller is operable to activate the first set of sensing components, the second set of sensing components, the third set of sensing components, and the fourth set of sensing components independently of one another.

20. An electronic memory apparatus, comprising:
a first set of memory cells;
a second set of memory cells;
a first set of sensing components;
a second set of sensing components; and
a controller in electronic communication with the first set of memory cells, the second set of memory cells, the first set of sensing components, and the second set of sensing components, wherein the controller is operable to:
select the first set of memory cells and the second set of memory cells for a read operation using a word line that is in electronic communication with the first set of memory cells and the second set of memory cells;
activate the first set of sensing components correspo

Assignees

• Micron Technology Inc

Inventors

• Kawamura Christopher John

Classifications

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/2253

  Address circuits or decoders · CPC title

• G11C11/2259

  Cell access · CPC title