Execution using multiple page tables

Patent metadata

Field	Value
Publication number	US-9697120-B2
Application number	US-201213997642-A
Country	US
Kind code	B2
Filing date	May 9, 2012
Priority date	May 9, 2012
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Embodiments of techniques and systems for execution of code with multiple page tables are described. In embodiments, a heterogenous system utilizing multiple processors may use multiple page tables to selectively execute appropriate ones of different versions of executable code. The system may be configured to support use of function pointers to virtual memory addresses. In embodiments, a virtual memory address may be mapped, such as during a code fetch. In embodiments, when a processor seeks to perform a code fetch using the function pointer, a page table associated with the processor may be used to translate the virtual memory address to a physical memory address where code executable by the processor may be found. Usage of multiple page tables may allow the system to support function pointers while utilizing only one virtual memory address for each function that is pointed to. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. One or more non-transitory computer-readable storage media comprising instructions embodied therein that, in response to execution by a computer device having a first computer processor with a first instruction set architecture and a second computer processor with a second instruction set architecture that differs from the first instruction set architecture, cause the computer device to operate a virtual machine manager to facilitate selective invocation of a first version of a function for execution by the first computer processor or a second version of the same function for execution by the second computer processor, wherein to facilitate, the virtual machine manager is to translate a virtual memory address in a function pointer of the function associated with a code fetch by the first or the second processor into corresponding first or second physical memory address of a first or a second physical memory location of a first or a second physical memory region having the first or the second version of the same function respectively implemented with first and second plurality of instructions of the first or second instruction set architecture, wherein to translate the virtual memory address, the virtual machine manager is to use a selected one of a first page table or a second page table correspondingly associated with the first and second processors, wherein which of the first and second page tables is used depends on whether the code fetch is associated with the first or the second processor.

2. The one or more computer-readable storage media of claim 1 , wherein:
the first page table maps the virtual memory address in the function pointer of the function associated with the code fetch to the first physical memory address, when the code fetch is associated with the first processor, and
the second page table maps the virtual memory address in the function pointer of the function associated with the code fetch to the second physical memory address, when the code fetch is associated with the second processor.

3. The one or more computer-readable storage media of claim 2 , wherein the first physical memory address is associated with the first physical memory location of the first physical memory region having the first version of the function implemented with instructions of the first instruction set architecture of the first processor, and the second physical memory address is associated with the second physical memory location of the second physical memory region having the second version of the function implemented with instructions of the second instruction set architecture of the second processor, wherein the first and second physical memory regions are different physical memory regions.

4. The one or more computer-readable storage media of claim 3 , wherein the first and second page tables are to map virtual memory addresses associated with a common virtual memory data region to physical memory addresses of a common physical memory region.

5. The one or more computer-readable storage media of claim 3 , wherein the first version of the function implemented with instructions of the first instruction set architecture, and the second version of the function implemented with instructions of the second instruction set architecture are each generated from common source code.

6. The one or more computer-readable storage media of claim 5 , wherein the instructions are to further cause the computer device to operate a loader to load the first version of the function and the second version of the function into the corresponding first and second physical memory regions.

7. The one or more computer-readable storage media of claim 6 , wherein the loader is to facilitate configuration of the first and second page tables to map the virtual memory address of the function point of the function associated with the code fetch to the corresponding first and second physical memory addresses.

8. The one or more computer-readable storage media of claim 7 , wherein the loader is to facilitate configuration of the first and second page tables to map virtual memory addresses associated with a common virtual memory region including the virtual memory address associated with the code fetch to physical memory addresses of the first and second physical memory regions.

9. The one or more computer-readable storage media of claim 8 , wherein the loader is to select a size for the common virtual memory region based at least in part on respective sizes of the first version of the function and the second version of the function.

10. The one or more computer-readable storage media of claim 9 , wherein the loader is to select the size for the common virtual memory region based at least in part on a larger of a size of the first version of the function and a size of the second version of the function.

11. One or more non-transitory computer-readable storage media comprising instructions embodied therein that, in response to execution by a computer device comprising a first computer processor with a first instruction set architecture and a second computer processor with a second instruction set architecture that differs from the first instruction set architecture, cause the computer device to operate a loader to facilitate selective invocation of either a first version a function or a second version of the same function for execution by either the first computer processor or the second computer processor, wherein to facilitate, the loader is to:
respond to a request to load executable code for the function into memory on the computer device, wherein the executable code of the first version of the function is implemented with a first plurality of instructions of the first instruction set architecture, and the executable code of the second version of the same function is implemented with a second plurality of instructions of the second instruction set architecture, wherein response to the request includes performance of a load of the executable code of the first version of the function, and the executable code of the second version of the same function into physical memory of the computer device at respective first and second physical memory regions;
facilitate configuration of first and second page tables for use in translating a virtual memory address in a function pointer of the function associated with a code fetch made by the corresponding first and second computer processors, wherein the first and second page tables are to respectively map the virtual memory address in the function pointer to first and second physical memory addresses in the corresponding first and second physical memory regions respectively having the executable code of the first and second versions of the same function.

12. The one or more computer-readable storage media of claim 11 , wherein the loader is to facilitate configuration of the first and second page tables through facilitation of configuration of the first and second page tables to respectively map virtual memory addresses associated with a common virtual memory region, including the virtual memory address in the function pointer of the function, to physical memory addresses of the first and second physical memory regions.

13. The one or more computer-readable storage media of claim 12 , wherein the loader is to select a size for the common virtual memory region based on respective sizes of the first version of the executable code and the second version of the executable code.

14. The one or more computer-readable storage media of claim 13 , wherein the loader is to select the size based at least in part on a larger of a size of the fir

Assignees

• Macpherson Mike B
• Intel Corp

Inventors

• Macpherson Mike B

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F9/45554

  Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F2212/151

  Emulated environment, e.g. virtual machine · CPC title