Bonded assembly containing laterally bonded bonding pads and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11239204-B2
Application number	US-201916694400-A
Country	US
Kind code	B2
Filing date	Nov 25, 2019
Priority date	Nov 25, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.

First claim

The invention claimed is:

1. A bonded assembly comprising:
a first semiconductor die comprising first semiconductor devices and first bonding pads having a top surface facing away from the first semiconductor devices, a bottom surface facing the first semiconductor devices and at least one sidewall between the top surface and the bottom surface; and
a second semiconductor die comprising second semiconductor devices and second bonding pads having a top surface facing away from the second semiconductor devices, a bottom surface facing the second semiconductor devices and at least one sidewall between the top surface and the bottom surface;
wherein the sidewalls of the second bonding pads are bonded to the respective sidewalls of the first bonding pads.

2. The bonded assembly of claim 1 , wherein:
the first semiconductor die further comprises a first substrate having a first major surface, and first metal interconnect structures embedded in first dielectric material layers that laterally extend along horizontal directions parallel to the first major surface, wherein the first bonding pads are electrically connected to a respective node of the first semiconductor devices through a respective subset of the first metal interconnect structures;
the second semiconductor die further comprises a second substrate having a second major surface, and second metal interconnect structures embedded in second dielectric material layers that laterally extend along the horizontal directions parallel to the second major surface, wherein the second bonding pads are electrically connected to a respective node of the second semiconductor devices through a respective subset of the second metal interconnect structures; and
the second bonding pads are bonded to a respective one of the first bonding pads at a respective non-horizontal bonding interface that is at an angle greater than zero degrees relative to a horizontal plane including the horizontal directions.

3. The bonded assembly of claim 2 , wherein:
non-horizontal bonding interfaces between bonded pairs of a respective first bonding pad and a respective second bonding pad are located at multiple levels having different vertical separation distances from the first substrate;
the first bonding pads comprise first proximal bonding pads that are vertically spaced from the first substrate by a first proximal vertical separation distance and first distal bonding pads that are vertically spaced from the first substrate by a first distal vertical separation distance that is greater than the first proximal vertical separation distance;
the second bonding pads comprise second proximal bonding pads that are vertically spaced from the second substrate by a second proximal vertical separation distance and second distal bonding pads that are vertically spaced from the second substrate by a second distal vertical separation distance that is greater than the second proximal vertical separation distance;
the first proximal bonding pads are bonded to a respective one of the second distal bonding pads; and
the first distal bonding pads are bonded to a respective one of the second proximal bonding pads.

4. The bonded assembly of claim 3 , wherein a difference between the first distal vertical separation distance and the first proximal vertical separation distance is at least a thickness of the first proximal bonding pads.

5. The bonded assembly of claim 3 , wherein:
each of the first bonding pads has a respective distal horizontal surface that faces the second substrate and contacting a horizontal surface of a respective first dielectric cover liner; and
each of the second bonding pads has a respective distal horizontal surface that faces the first substrate and contacting a horizontal surface of a respective second dielectric cover liner.

6. The bonded assembly of claim 5 , wherein one of the first proximal bonding pads has an areal overlap with one of the second bonding pads, and is vertical spaced from the one of the second bonding pads by a stack of one of the first dielectric cover liners and one of the second dielectric cover liners.

7. The bonded assembly of claim 5 , wherein each of the first dielectric cover liners and the second dielectric cover liners has a thickness that is less than one half of a minimum thickness of the first bonding pads and is less than one half of a minimum thickness of the second bonding pads.

8. The bonded assembly of claim 5 , wherein:
each of the first bonding pads is vertically spaced from the second semiconductor die by a vertical separation distance that is the same as a thickness of a respective one of the first dielectric cover liners; and
the first proximal bonding pads are vertically spaced from the second semiconductor die by a first bonding dielectric layer that overlies the first proximal boding pads and underlies a subset of the first bonding pads that are more distal from the first substrate than the first proximal bonding pads are from the first substrate.

9. The bonded assembly of claim 3 , wherein each of the first dielectric material layers that contacts sidewalls of the first bonding pads comprises a horizontal surface that contacts a horizontal surface of a respective one of the second dielectric material layers.

10. The bonded assembly of claim 3 , wherein:
the first proximal bonding pads are embedded in a first proximal bonding dielectric layer;
the first distal bonding pads are embedded in a first distal bonding dielectric layer;
the second proximal bonding pads are embedded in a second proximal bonding dielectric layer that contacts the first distal bonding dielectric layer; and
the second distal bonding pads are embedded in a second distal bonding dielectric layer that contacts the first proximal bonding dielectric layer.

11. The bonded assembly of claim 1 , wherein the sidewalls of a first set of second bonding pads are bonded to sidewalls of the respective first bonding pads, and the top surfaces of a second set of second bonding pads are bonded to top surfaces of additional respective first bonding pads, such that the second bonding pads are bonded to the respective first bonding pads in three dimensions.

12. The bonded assembly of claim 1 , wherein the first semiconductor devices comprise three-dimensional memory devices, and the second semiconductor devices comprise driver circuit devices for the three-dimensional memory devices.

13. A method of forming a bonded assembly, comprising:
providing a first semiconductor die comprising first semiconductor devices and first bonding pads having a top surface facing away from the first semiconductor devices, a bottom surface facing the first semiconductor devices and at least one exposed sidewall between the top surface and the bottom surface;
a second semiconductor die comprising second semiconductor devices and second bonding pads having a top surface facing away from the second semiconductor devices, a bottom surface facing the second semiconductor devices and at least one exposed sidewall between the top surface and the bottom surface; and
bonding the exposed sidewalls of the second bonding pads to the respective exposed sidewalls of the first bonding pads.

14. The method of claim 13 , wherein:
the first semiconductor die further comprises a first substrate having a first major surface, and first metal interconnect structures embedded in first dielectric material layers that laterally extend along horizontal directions parallel to the first major surface, wherein the first bonding pads are electrically connected to a respective node of the first semiconductor devices through a respective subset

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Chen
• Rabkin Peter
• Chen Yangyin
• Higashitani Masaaki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title