Back end memory integration process

Patent metadata

Field	Value
Publication number	US-11239086-B2
Application number	US-201916396226-A
Country	US
Kind code	B2
Filing date	Apr 26, 2019
Priority date	May 14, 2018
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

First claim

What is claimed is:

1. A substrate processing method, comprising:
forming a metallic bottom contact on a substrate;
depositing a non-metallic interlayer dielectric material on the substrate;
forming a via within the non-metallic interlayer dielectric material, wherein the via extends from the metallic bottom contact in a first region;
etching a zero mark in the non-metallic interlayer dielectric material in a second region apart from the first region to a depth less than a total thickness of the non-metallic interlayer dielectric material, wherein the etching a zero mark in the non-metallic interlayer dielectric material is performed prior to deposition of any of a touch layer, a memory stack comprising a plurality of films, wherein at least one film of the plurality of films is a magnesium oxide containing film, or a hardmask;
depositing the touch layer over the non-metallic interlayer dielectric material and the via in the first region and the second region;
depositing the memory stack over the touch layer in the first region and the second region; and
depositing the hardmask over the memory stack in the first region and the second region.

2. The method of claim 1 , wherein the etching a zero mark comprises masking the first region and etching the non-metallic interlayer dielectric material in the second region.

3. The method of claim 2 , wherein the etching the non-metallic interlayer dielectric material in the second region comprises exposing the non-metallic interlayer dielectric material to an anisotropic oxide etching process.

4. The method of claim 1 , wherein the zero mark has a width of between about 1 μm and about 2 μm.

5. The method of claim 1 , wherein the metallic bottom contact is formed on a metallic portion of the substrate and the via extends from the metallic bottom contact through the non-metallic interlayer dielectric material.

6. The method of claim 1 , wherein the touch layer, the memory stack, and the hardmask are conformally deposited over the non-metallic interlayer dielectric material in the first region and the second region.

7. The method of claim 1 , wherein the touch layer is selected from the group consisting of a TaN material, a Ta material, and a W material.

8. A substrate processing method, comprising:
forming a bottom contact on a substrate;
depositing a non-metallic interlayer dielectric material on the substrate;
forming a metallic via extending from the bottom contact through the non-metallic interlayer dielectric material in a first region;
etching a zero mark in the non-metallic interlayer dielectric material in a second region apart from the first region to a depth less than a total thickness of the non-metallic interlayer dielectric material, wherein the etching a zero mark in the non-metallic interlayer dielectric material is performed prior to conformal deposition of any of a touch layer, a memory stack comprising a plurality of films, wherein at least one film of the plurality of films is a magnesium oxide containing film, or a hardmask;
conformally depositing the touch layer over the substrate in the first region and the second region;
conformally depositing the memory stack over the touch layer in the first region and the second region;
conformally depositing the hardmask over the memory stack in the first region and the second region;
patterning at least the first region; and
sequentially etching the hardmask, the memory stack, and the touch layer after patterning the first region.

9. The method of claim 8 , wherein the etching a zero mark comprises masking the first region and etching the non-metallic interlayer dielectric material in the second region.

10. The method of claim 9 , wherein the etching the non-metallic interlayer dielectric material in the second region comprises exposing the substrate to an anisotropic oxide etching process.

11. The method of claim 8 , wherein the zero mark has a width of between about 1 μm and about 2 μm.

12. A substrate processing method, comprising:
forming a bottom contact on a substrate;
depositing a non-metallic interlayer dielectric material on the substrate;
etching the non-metallic interlayer dielectric material to expose the bottom contact;
forming a metallic via extending from the bottom contact in a first region;
etching a zero mark in the non-metallic interlayer dielectric material in a second region apart from the first region to a depth less than a total thickness of the non-metallic interlayer dielectric material, wherein the etching a zero mark in the non-metallic interlayer dielectric material is performed prior to conformal deposition of any of a touch layer, a memory stack comprising a plurality of films, wherein at least one film of the plurality of films is a magnesium oxide containing film, or a hardmask;
conformally depositing the touch layer over the non-metallic interlayer dielectric material and the metallic via in the first region and the second region;
conformally depositing the memory stack over the touch layer in the first region and the second region;
conformally depositing the hardmask over the memory stack in the first region and the second region;
patterning at least the first region;
sequentially etching the hardmask, the memory stack, and the touch layer after patterning the first region to expose the non-metallic interlayer dielectric material;
depositing additional interlayer dielectric material and planarizing the additional interlayer dielectric material with the hardmask;
etching at least a portion of the hardmask to form a recess; and
depositing a top contact over the additional interlayer dielectric material and in the recess.

13. The method of claim 12 , wherein the etching a zero mark is an anisotropic oxide etch process.

14. The method of claim 12 , wherein the zero mark has a width of between about 1 μm and about 2 μm.

15. The method of claim 12 , wherein etching the non-metallic interlayer dielectric material to expose a bottom contact further comprises forming a recess, wherein the recess has a width at a top surface of the bottom contact which is less than a width of the top surface of the recess.

16. The method of claim 12 , wherein a width of the via structure at a top surface is less than a width of the touch layer at a top surface.

17. The method of claim 16 , wherein a difference between the width of the via structure at the top surface and the width of the touch layer at the top surface is less than one third of the width of the touch layer at the top surface.

18. The method of claim 1 , further comprising:
patterning at least the first region; and
sequentially etching the hardmask, the memory stack, and the touch layer after patterning the first region.

Assignees

• Applied Materials Inc

Inventors

• Tseng Hsin-Wei
• Pakala Mahendra
• Xue Lin
• Ahn Jaesoo
• Amin Hassan Sajjad

Classifications

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W46/301

  for alignment · CPC title

• H10P50/644 Primary

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title