Silicon substrate containing integrated porous silicon electrodes for energy storage devices

Patent metadata

Field	Value
Publication number	US-11233288-B2
Application number	US-201816032317-A
Country	US
Kind code	B2
Filing date	Jul 11, 2018
Priority date	Jul 11, 2018
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A method of forming a semiconductor structure includes forming at least one trench in a non-porous silicon substrate, the at least one trench providing an energy storage device containment feature. The method also includes forming an electrical and ionic insulating layer disposed over a top surface of the non-porous silicon substrate. The method further includes forming, in at least a base of the at least one trench, a porous silicon layer of unitary construction with the non-porous silicon substrate. The porous silicon layer provides at least a portion of a first active electrode for an energy storage device disposed in the energy storage device containment feature.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming at least one trench in a non-porous silicon substrate, the at least one trench providing an energy storage device containment feature;
forming an electrical and ionic insulating layer disposed over a top surface of the non-porous silicon substrate;
forming, in a base of the at least one trench, a porous silicon layer of unitary construction with the non-porous silicon substrate;
forming a bottom current collector on at least a portion of a bottom surface of the non-porous silicon substrate, the portion of the bottom surface of the non-porous silicon substrate being aligned with the base of the at least one trench in which the porous silicon layer is formed, the bottom current collector being separated from the porous silicon layer by a non-porous silicon material of the non-porous silicon substrate;
wherein the porous silicon layer provides at least a portion of a first active electrode for an energy storage device disposed in the energy storage device containment feature;
wherein the electrical and ionic insulating layer is further disposed on sidewalls of the at least one trench;
wherein the non-porous silicon substrate comprises a p− silicon substrate, and wherein forming the porous silicon layer in the base of the at least one trench comprises:
forming a p+ type doped silicon region with a controlled doping level on an exposed portion of the non-porous silicon substrate in the base of the at least one trench via epitaxial layer growth of p+ type silicon;
cleaning the epitaxial layer of p+ type silicon; and
electrochemically etching the cleaned epitaxial layer to form the porous silicon layer;

wherein cleaning the epitaxial layer of p+ type silicon utilizes a solution of ammonium hydroxide:hydrogen peroxide:deionized water at a ratio of 1:1:5; and
wherein electrochemically etching the cleaned epitaxial layer to form the porous silicon layer comprises electrochemically etching the cleaned epitaxial layer in hydrofluoric acid.

2. The method of claim 1 , further comprising:
forming an electrolyte layer disposed over the porous silicon layer;
forming a second active electrode layer for the energy storage device containment feature disposed over the electrolyte layer;
forming a top current collector disposed over the second active electrode layer; and
forming an encapsulation layer disposed over the electrical and ionic insulating layer surrounding the top current collector.

3. The method of claim 2 , further comprising:
forming a first interfacial layer disposed between the porous silicon layer and the electrolyte layer; and
forming a second interfacial layer disposed between the electrolyte layer and the second active electrode layer.

4. The method of claim 1 , wherein:
forming the electrical and ionic insulating layer comprises blanket depositing an electrically and ionically insulating material over a top surface of the non-porous silicon substrate prior to forming the at least one trench;
forming the at least one trench in the non-porous silicon substrate comprises:
patterning a resist material over the electrically and ionically insulating material;
etching exposed portions of the electrically and ionically insulating material and underlying portions of the non-porous silicon substrate to form the at least one trench; and
removing remaining portions of the resist material; and

forming the porous silicon layer comprises forming the porous silicon layer in the base and sidewalls of the at least one trench.

5. The method of claim 4 , further comprising:
forming an electrolyte layer disposed over the porous silicon layer on the sidewalls and bases of the at least one trench;
forming a second active electrode layer for the energy storage device in a remaining space of the at least one trench between portions of the electrolyte layer;
forming a top current collector disposed over the second active electrode layer;
forming an encapsulation layer disposed over the electrical and ionic insulating layer surrounding the top current collector.

6. The method of claim 1 , wherein electrochemically etching the cleaned epitaxial layer in hydrofluoric acid comprises utilizing a hydrofluoric acid-based anodization etching treatment.

7. The method of claim 6 , wherein the hydrofluoric acid-based anodization etching treatment comprises etching in a solution of hydrofluoric acid for a designated period of time.

8. The method of claim 7 , wherein the solution of hydrofluoric acid comprises about 49% hydrofluoric acid.

9. The method of claim 7 , wherein the designated period of time is between about 10 seconds and about 20 minutes.

10. The method of claim 7 , wherein the designated period of time is less than about 500 seconds.

11. The method of claim 7 , wherein the hydrofluoric acid-based anodization etching treatment comprises etching in a solution of hydrofluoric acid for the designated period of time at a specific current density normalized to a surface area of the base of the at least one trench.

12. The method of claim 11 , wherein the specific current density is less than 1 to greater than 10 milliamperes per square centimeter.

13. The method of claim 1 , wherein the controlled doping level of the p+ type doped silicon region comprises a Boron doping in the range of about 10 18 /cm 3 to greater than 10 20 /cm 3 .

14. The method of claim 1 , wherein the controlled doping level of the p+ type doped silicon region comprises a Boron doping in the range of about 1 to 3 19 /cm 3 .

15. The method of claim 2 , wherein the electrolyte layer comprises a material that is ionically conducting to lithium.

16. The method of claim 2 , wherein the second active electrode layer comprises a lithium-containing material.

17. The method of claim 2 , wherein each of the top current collector and the bottom current collector comprises at least one of copper, nickel, aluminum, titanium, tungsten, platinum, and gold.

18. The method of claim 2 , wherein the encapsulation layer comprises silicon nitride.

19. The method of claim 3 , wherein the first interfacial layer comprises at least one of lithium metal, molten lithium metal and a lithiated active planar anode layer.

20. The method of claim 3 , wherein the second interfacial layer comprises at least one of lithium phosphorus oxygen, aluminum oxide, lithium niobium oxide, gold, indium and a lithium silicon composite.

Assignees

• IBM

Inventors

• Collins John
• De Souza Joel P
• Sadana Devendra K

Classifications

• H01M4/044 Primary

  Activating, forming or electrochemical attack of the supporting material · CPC title

• H01M50/14

  for protecting against damage caused by external factors · CPC title

• H01M50/133

  Thickness · CPC title

• H01M50/117

  Inorganic material · CPC title

• H01M2220/30

  Batteries in portable systems, e.g. mobile phone, laptop · CPC title