Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11233150-B2
Application number	US-202016910819-A
Country	US
Kind code	B2
Filing date	Jun 24, 2020
Priority date	Oct 1, 2019
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first semiconductor pattern spaced apart from the substrate;
a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, the first antioxidant pattern including a first semiconductor material film doped with a first impurity; and
a field insulating film on the substrate, the field insulating film covering at least a part of a side wall of the first semiconductor pattern; and
a protruding pattern protruding from the substrate,
wherein a portion of field insulating film is disposed between the first antioxidant pattern and the protruding pattern.

2. The semiconductor device of claim 1 , wherein the first antioxidant pattern includes silicon, silicon germanium, or both silicon and silicon germanium.

3. The semiconductor device of claim 1 , wherein the first impurity includes at least one of oxygen (O), nitrogen (N), and carbon (C).

4. The semiconductor device of claim 1 , further comprising:
a second antioxidant pattern extending along an upper surface of the protruding pattern, wherein
the second antioxidant pattern includes a second semiconductor material film doped with a second impurity, and
the second antioxidant pattern is spaced apart from the first antioxidant pattern.

5. The semiconductor device of claim 1 , wherein
the field insulating film includes a filling insulating film and a stress insulating film,
the stress insulating film includes an oxide containing germanium, and
the stress insulating film is between the first antioxidant pattern and the protruding pattern.

6. The semiconductor device of claim 1 , wherein an upper part of the protruding pattern has a triangular shape.

7. The semiconductor device of claim 1 , wherein
the first antioxidant pattern includes a first sub-pattern and a second sub-pattern,
the first sub-pattern is undoped, and
the second sub-pattern is doped with the first impurity.

8. The semiconductor device of claim 1 , wherein
the first antioxidant pattern includes a plurality of first sub-patterns and a plurality of second sub-patterns alternatively stacked,
the plurality of first sub-patterns are undoped, and
the plurality of second sub-patterns are doped.

9. The semiconductor device of claim 1 , further comprising:
a germanium deposition pattern, wherein
the field insulating film includes a filling insulating film and a stress insulating film,
the stress insulating film includes an oxide containing germanium, and
the germanium deposition pattern is in the stress insulating film.

10. The semiconductor device of claim 1 , wherein
the field insulating film includes a filling insulating film and a stress insulating film,
the stress insulating film includes an oxide containing germanium,
the first antioxidant pattern includes silicon germanium, and
a concentration of germanium in the stress insulating film is higher than a concentration of germanium in the first antioxidant pattern.

11. The semiconductor device of claim 1 , further comprising:
a fin liner, wherein
the fin liner extends along at least a part of the side wall of the first semiconductor pattern, and
the fin liner extends between the field insulating film and the first semiconductor pattern.

12. The semiconductor device of claim 11 , wherein the fin liner further includes a protruding part protruding in a direction perpendicular from the side wall of the first semiconductor pattern.

13. The semiconductor device of claim 1 , further comprising:
a second semiconductor pattern over the first semiconductor pattern, wherein
the second semiconductor pattern is spaced apart from the first semiconductor pattern.

14. The semiconductor device of claim 1 , further comprising:
a gate electrode on the first semiconductor pattern, wherein
the first semiconductor pattern extends in a first direction, and
the gate electrode extends in a second direction that intersects the first direction.

15. A semiconductor device comprising:
a substrate;
a first semiconductor pattern spaced apart from the substrate;
a field insulating film on the substrate and covering at least a part of a side wall of the first semiconductor pattern,
the field insulating film including a filling insulating film and a stress insulating film, the stress insulating film including an oxide containing germanium; and
a fin liner extending along at least a part of the side wall of the first semiconductor pattern and extending between the field insulating film and the first semiconductor pattern,
the fin liner being arranged so the fin liner is not in contact with the substrate.

16. The semiconductor device of claim 15 , further comprising:
an antioxidant pattern spaced apart from the substrate and extends along a bottom surface of the first semiconductor pattern,
wherein the antioxidant pattern includes a semiconductor material film doped with impurity.

17. The semiconductor device of claim 15 , further comprising:
a protruding pattern protruding from the substrate, wherein
the field insulating film covers the protruding pattern, and
a height of a lower surface of the fin liner is higher than a height of an uppermost part of the protruding pattern relative to an upper surface of the substrate.

18. The semiconductor device of claim 15 , wherein a height of a lower surface of the fin liner is the same as or lower than the height of a bottom surface of the first semiconductor pattern relative to an upper surface of the substrate.

19. The semiconductor device of claim 15 , further comprising:
a second semiconductor pattern horizontally spaced apart from the substrate,
wherein the fin liner includes a first portion on a side wall of the first semiconductor pattern, a second portion on a side wall of the second semiconductor pattern, and a connecting portion for connecting the first portion and the second portion.

20. The semiconductor device of claim 15 , wherein
a bottom surface of the first semiconductor pattern contacts the field insulating film,
the field insulating film includes an oxidation-inhibiting impurity including at least one of carbon and nitrogen, and
a concentration of the oxidation-inhibiting impurity in the field insulating film decreases as it goes away from the bottom surface of the first semiconductor pattern.

21. The semiconductor device of claim 15 , wherein the fin liner includes a silicon nitride film.

22. The semiconductor device of claim 15 , wherein the fin liner includes a semiconductor material film doped with impurity.

23. The semiconductor device of claim 15 , further comprising:
a second semiconductor pattern over the first semiconductor pattern and spaced apart from the first semiconductor pattern; and
a gate electrode on the field insulating film,
wherein the gate electrode wraps around the second semiconductor pattern.

24. The semiconductor device of claim 15 , wherein the stress insulating film is between the first semiconductor pattern and the substrate.

25. A semiconductor device comprising:
a substrate;
a protruding pattern protruding from the substrate;
a first semiconductor pattern spaced apart from the protruding pattern;
a first antioxidant pattern contacting the first semiconductor pattern and extending along a bottom surface of the first semiconductor pattern, the first antioxidant pattern ex

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jin Bum
• Kim Gyeom
• Kim Da Hye
• Kim Jae Mun
• Shin Il Gyou
• Lee Seung Hun
• Choi Kyung In

Classifications

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D30/791

  Arrangements for exerting mechanical stress on the crystal lattice of the channel regions · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title