Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11227952-B2
Application number	US-202016743206-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	May 27, 2019
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin shaped active region protruding from a substrate and extending in a first direction;
a plurality of semiconductor patterns that are on and are spaced apart from an upper surface of the fin shaped active region, the plurality of semiconductor patterns comprising a channel region and an uppermost semiconductor pattern that is a farthest one of the plurality of semiconductor patterns from the upper surface of the fin shaped active region;
a gate electrode extending on the plurality of semiconductor patterns in a second direction that is perpendicular to the first direction, the gate electrode comprising a main gate portion that extends on the uppermost semiconductor pattern in the second direction and a sub-gate portion that is between two adjacent ones of the plurality of semiconductor patterns; and
source/drain regions that are on opposing sides of the gate electrode, respectively, and are connected to the plurality of semiconductor patterns,
wherein the sub-gate portion comprises:
a sub-gate center portion; and
sub-gate edge portions that comprise opposing end portions of the sub-gate portion, respectively, in the second direction,

wherein, in a first horizontal cross-sectional view, a first width of the sub-gate center portion in the first direction is less than a second width of one of the sub-gate edge portions in the first direction, and
wherein each of the source/drain regions comprises a protrusion portion protruding toward a respective one of the sub-gate edge portions.

2. The integrated circuit device of claim 1 , wherein each of the sub-gate edge portions comprises a tail portion that is adjacent to a respective one of the source/drain regions.

3. The integrated circuit device of claim 2 , further comprising:
spacer structures on opposing sidewalls of the main gate portion, respectively, the spacer structures overlapping the tail portions of the sub-gate edge portions in the second direction; and
a gate insulation layer that is between the tail portions of the sub-gate edge portions and the spacer structures.

4. The integrated circuit device of claim 3 , wherein each of the spacer structures contacts a respective one of the protrusion portions of the source/drain regions.

5. The integrated circuit device of claim 1 ,
wherein each of the plurality of semiconductor patterns comprises a pair of concave sidewalls opposite each other in the first direction, and the pair of concave sidewalls of each of the plurality of semiconductor patterns are recessed inwardly, and
wherein the pair of concave sidewalls of each of the plurality of semiconductor patterns respectively contact the protrusion portions of the source/drain regions.

6. The integrated circuit device of claim 1 , wherein the main gate portion comprises a main gate connection portion that is adjacent to the plurality of semiconductor patterns and does not vertically overlap the plurality of semiconductor patterns, and
a third width of the main gate connection portion in the first direction is less than the second width of the one of the sub-gate edge portions in the first direction.

7. The integrated circuit device of claim 6 ,
wherein each of the plurality of semiconductor patterns comprises a tail portion adjacent to the main gate connection portion,
wherein the tail portion of each of the plurality of semiconductor patterns protrudes outwardly in the first direction beyond a sidewall of the main gate connection portion, and
wherein the tail portion of each of the plurality of semiconductor patterns is thinner than a main portion of each of the plurality of semiconductor patterns in the second direction.

8. The integrated circuit device of claim 1 , further comprising a spacer structure comprising a first spacer and a second spacer sequentially stacked on a sidewall of the main gate portion,
wherein the second spacer comprises a lateral extension portion extending on the uppermost semiconductor pattern in the first direction away from the sidewall of the main gate portion.

9. The integrated circuit device of claim 8 , wherein each of the sub-gate edge portions comprises a tail portion that is adjacent to a respective one of the source/drain regions, and
the tail portion of one of the sub-gate edge portions overlaps the lateral extension portion of the second spacer in the second direction.

10. The integrated circuit device of claim 1 , wherein the second width of the one of the sub-gate edge portions monotonically increases along the second direction away from the sub-gate center portion.

11. An integrated circuit device comprising:
a fin shaped active region protruding from a substrate and extending in a first direction;
a plurality of semiconductor patterns that are on and are spaced apart from an upper surface of the fin shaped active region, the plurality of semiconductor patterns comprising a channel region and an uppermost semiconductor pattern that is a farthest one of the plurality of semiconductor patterns from the upper surface of the fin shaped active region;
a gate electrode extending on the plurality of semiconductor patterns in a second direction that is perpendicular to the first direction, the gate electrode comprising a main gate portion that extends on the uppermost semiconductor pattern in the second direction and a sub-gate portion that is between two adjacent ones of the plurality of semiconductor patterns;
a spacer structure on a sidewall of the main gate portion; and
source/drain regions that are on opposing sides of the gate electrode, respectively, and are connected to the plurality of semiconductor patterns, each of the source/drain regions comprising a protrusion portion protruding toward the gate electrode,
wherein each of opposing edge portions of the sub-gate portion in the second direction comprises a tail portion adjacent to a respective one of the source/drain regions,
wherein the spacer structure overlaps the tail portion of the sub-gate portion in the second direction, and
wherein the integrated circuit device further comprises a gate insulation layer that is between the tail portion of the sub-gate portion and the spacer structure.

12. The integrated circuit device of claim 11 ,
wherein the spacer structure contacts the protrusion portion of one of the source/drain regions.

13. The integrated circuit device of claim 12 , wherein the tail portion of the sub-gate portion overlaps the spacer structure in the second direction.

14. The integrated circuit device of claim 11 ,
wherein the sub-gate portion comprises:
a sub-gate center portion; and
sub-gate edge portions that comprise the opposing edge portions of the sub-gate portion, respectively, in the second direction,

wherein the main gate portion comprises a main gate connection portion that is adjacent to the plurality of semiconductor patterns and does not vertically overlap the plurality of semiconductor patterns, and
wherein in a horizontal cross-sectional view, both a first width of the sub-gate center portion in the first direction and a third width of the main gate connection portion in the first direction are less than a second width of one of the sub-gate edge portions in the first direction.

15. The integrated circuit device of claim 11 , wherein each of the tail portions of the sub-gate portion is a taper portion protruding toward the respective one of the source/drain regions.

16. The integrated circuit device of claim 11 , wherein the uppermost semiconductor pattern is wider in the first direction and thicker, in a third

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Seungmin
• Park Junbeom
• Suh Bongseok
• Yang Junggil

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/6215

  having multiple independently-addressable gate electrodes · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D86/215

  comprising FinFETs · CPC title