Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement

Patent metadata

Field	Value
Publication number	US-10211307-B2
Application number	US-201715653068-A
Country	US
Kind code	B2
Filing date	Jul 18, 2017
Priority date	Jul 18, 2017
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
forming a first cover layer over the sacrificial gate structure and a second cover layer over the first cover layer;
forming a source/drain epitaxial layer on opposing sides of the sacrificial gate structure;
after the source/drain epitaxial layer is formed, removing the second cover layer, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed;
removing part of the first semiconductor layers in the gap, thereby forming spaces between the second semiconductor layers; and
filling the spaces with a first insulating material,
wherein the first insulating material is further formed on the source/drain epitaxial layer and the first cover layer.

2. The method of claim 1 , wherein one or more voids are formed in the first insulating material between the second semiconductor layers.

3. The method of claim 2 , wherein the one or more voids are in contact with the second semiconductor layers.

4. The method of claim 1 , wherein the first insulating material is a low-k dielectric material.

5. The method of claim 1 , wherein the first cover layer is made of a first dielectric material and the second cover layer is made of a second dielectric material different from the first dielectric material.

6. The method of claim 5 , wherein the first dielectric material is a low-k dielectric material.

7. The method of claim 5 , wherein the first dielectric material is one selected from the group consisting of SiOC and SiOCN.

8. The method of claim 5 , wherein the second dielectric material is one selected from the group consisting of silicon nitride, SiON and SiCN.

9. The method of claim 8 , wherein:
the second dielectric material is one selected from the group consisting of silicon nitride, and
in the removing the second cover layer, the second cover layer is removed by using H 3 PO 4 .

10. The method of claim 1 , wherein the forming the source/drain epitaxial layer includes:
recessing a part of the fin structure not covered by the sacrificial gate structure; and
forming a third semiconductor layer over the recessed fin structure as the source/drain epitaxial layer,
wherein the third semiconductor layer is made of a different semiconductor material than the second semiconductor layers.

11. The method of claim 1 , further comprising, after the first insulating material is formed:
removing the sacrificial gate structure, thereby exposing a part of the fin structure;
removing the first semiconductor layers from the exposed fin structure, thereby forming channel layers including the second semiconductor layers; and
forming a gate dielectric layer and a gate electrode layer around the channel layers.

12. The method of claim 11 , wherein the gate electrode layer is in contact with the first insulating material and isolated from the source/drain epitaxial layer by the first insulating material.

13. The method of claim 1 , wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.

14. A method of manufacturing a semiconductor device, comprising:
forming a fin structure having a bottom part and a stacked part in which first semiconductor layers and second semiconductor layers are alternately stacked over the bottom part;
forming a sacrificial gate structure over the fin structure;
forming a first cover layer over the sacrificial gate structure and a second cover layer over the first cover layer, the second cover layer being made of a different material than the first cover layer;
forming a source/drain epitaxial layer over the bottom part of the fin structure;
after the source/drain epitaxial layer is formed, removing the second cover layer, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed;
removing part of the first semiconductor layers in the gap, thereby forming spaces between the second semiconductor layers;
filling the spaces with a first insulating material, thereby forming insulating spacers,
wherein the first cover layer remains over the sacrificial gate structure during the filling the spaces with the first insulating material;
after the insulating spacers are formed, removing the sacrificial gate structure, thereby exposing a part of the fin structure;
removing the first semiconductor layers from the exposed fin structure, thereby forming channel layers including the second semiconductor layers; and
forming a gate dielectric layer and a gate electrode layer around the channel layers.

15. The method of claim 14 , wherein end faces of the insulating spacers over the bottom part of the fin structure in contact with the source drain epitaxial layer are vertically aligned.

16. The method of claim 14 , wherein one or more voids are formed in the first insulating material between the second semiconductor layers.

17. The method of claim 14 , wherein no void is formed in the first insulating material between the second semiconductor layers.

18. The method of claim 14 , wherein the first insulating material is one selected from the group consisting of SiOC and SiOCN.

19. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked,
wherein the first semiconductor layers are formed of a first semiconductor material composition and the second semiconductor layers are formed of a second semiconductor material composition, and the first semiconductor material composition and the second semiconductor material composition are different;
forming a sacrificial gate structure over the fin structure;
forming a first cover layer over the sacrificial gate structure and a second cover layer over the first cover layer;
forming a source/drain epitaxial layer on opposing sides of the sacrificial gate structure;
after the source/drain epitaxial layer is formed, removing the second cover layer, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed;
removing part of the first semiconductor layers in the gap, thereby forming spaces between the second semiconductor layers; and
filling the spaces with a first insulating material,
wherein the first insulating material is in direct contact with the first semiconductor material composition of the first semiconductor layer and the second semiconductor material composition of the second semiconductor layer.

20. The method of claim 19 , wherein one or more voids are formed in the first insulating material between the second semiconductor layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Wang Chih-Hao
• Tsai Ching-Wei
• Cheng Kuan-Lun

Classifications

• H01L29/66795

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/42392 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic