Thin reference layer for STT MRAM

Patent metadata

Field	Value
Publication number	US-11223010-B2
Application number	US-201916409905-A
Country	US
Kind code	B2
Filing date	May 13, 2019
Priority date	Apr 8, 2016
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

Techniques relate to forming a magnetic tunnel junction (MTJ). A synthetic antiferromagnetic reference layer is adjacent to a tunnel barrier layer. The synthetic antiferromagnetic reference layer includes a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer. A magnetic free layer is adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer. The synthetic antiferromagnetic reference layer has a thickness of at least one of 3 nanometers (nm), 4 nm, and 3-4 nm.

First claim

What is claimed is:

1. A semiconductor device comprising:
a synthetic antiferromagnetic reference layer in direct contact with both a tunnel barrier layer and a seed layer, the synthetic antiferromagnetic reference layer including a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a bottom magnetic layer, a middle spacer layer, and a top magnetic layer, the middle spacer layer of the synthetic antiferromagnetic reference layer in direct contact with both the tunnel barrier layer and the seed layer being in direct contact with both the bottom and top magnetic layers and being a multilayer structure comprising Ta, W, and Mo, the first magnetic layer of the synthetic antiferromagnetic reference layer having the multilayer structure comprising Ta, W, and Mo being in direct contact with both the reference spacer layer and the seed layer; and
a magnetic free layer adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer, the middle spacer layer with the multilayer structure comprising Ta, W, and Mo and the free magnetic layer sandwiching the reference spacer layer in between, the middle spacer layer with the multilayer structure comprising Ta, W, and Mo and the seed layer sandwiching the first magnetic layer in between;
wherein the synthetic antiferromagnetic reference layer has a thickness selected from the group consisting of about 3 nanometers (nm), about 4 nm, and about 3 to 4 nm.

2. The semiconductor device of claim 1 , wherein a sandwich of the synthetic antiferromagnetic reference layer, the tunnel barrier layer, and the magnetic free layer together form a magnetic tunnel junction (MTJ).

3. The semiconductor device of claim 1 , wherein the first magnetic layer comprises a thickness as small as about 0.5 nm.

4. The semiconductor device of claim 1 , wherein the first magnetic layer includes Co.

5. The semiconductor device of claim 1 , wherein the synthetic antiferromagnetic reference layer consists of the first magnetic layer, the second magnetic layer, and the reference spacer layer.

6. The semiconductor device of claim 1 , wherein the bottom magnetic layer includes Co.

7. The semiconductor device of claim 1 , wherein the bottom magnetic layer comprises a thickness ranging from about 0.2 to 2 nm.

8. The semiconductor device of claim 1 , wherein the middle spacer layer further comprises CoFeB.

9. The semiconductor device of claim 1 , wherein the middle spacer layer is disposed on top of the bottom magnetic layer, and the top magnetic layer is disposed on top of the middle spacer layer.

10. The semiconductor device of claim 1 , wherein:
the top magnetic layer is selected from the group consisting of Co, CoFeB, Fe, and CoFe.

11. The semiconductor device of claim 1 , wherein:
the top magnetic layer is a bilayer structure selected from the group consisting of of any two of Co, Fe, and B.

12. The semiconductor device of claim 1 , wherein:
the top magnetic layer comprises a thickness ranging from about 0.2 to 2 nm.

13. The semiconductor device of claim 1 , wherein the reference spacer layer is selected from the group consisting of Ir, Ru, Rh, and Os.

14. The semiconductor device of claim 1 , wherein the reference spacer layer comprises a thickness ranging from about 0.3 to 2 nm.

15. The semiconductor device of claim 1 , wherein the synthetic antiferromagnetic reference layer is formed on top of and in direct contact with a seed layer.

16. The semiconductor device of claim 15 , wherein the seed layer is selected from the group consisting of Ir, Ta, NiCr, Pd, Pt, and Ru.

17. The semiconductor device of claim 15 , wherein the seed layer comprises a thickness ranging from about 1 to 5 nm.

18. The semiconductor device of claim 1 , wherein:
the middle spacer layer is an alloy of materials.

19. The semiconductor device of claim 18 , wherein the middle spacer layer further comprises CoFeB.

20. The semiconductor device of claim 1 , wherein:
the middle spacer layer is about 2 nm.

Assignees

• IBM
• Samsung Electronics Co Ltd

Inventors

• Hu Guohan
• Kim Younghyun
• Worledge Daniel C

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H01L43/10

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic