Composite piezoelectric capacitor

Patent metadata

Field	Value
Publication number	US-11217392-B2
Application number	US-201916417346-A
Country	US
Kind code	B2
Filing date	May 20, 2019
Priority date	Jan 17, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

First claim

What is claimed is:

1. A composite field effect transistor, comprising:
a field effect transistor comprising a gate dielectric layer having a top surface;
a negative-capacitance piezoelectric stack; and
a conductive layer interposed between the gate dielectric layer and the negative-capacitance piezoelectric stack,
the negative-capacitance piezoelectric stack comprising:
a first piezoelectric layer;
a non-piezoelectric layer, on the first piezoelectric layer; and
a second piezoelectric layer on the non-piezoelectric layer,
the non-piezoelectric layer being interposed between the first piezoelectric layer and the second piezoelectric layer,

the first piezoelectric layer being composed of a first piezoelectric material;
the second piezoelectric layer being composed of a second piezoelectric material, different from the first piezoelectric layer; and
the negative-capacitance piezoelectric stack being operatively coupled to the top surface of the gate dielectric layer, and having an effective relative dielectric constant less than zero as a result of differences between the respective properties of the first piezoelectric material and the second piezoelectric material.

2. The composite field effect transistor of claim 1 , further comprising:
a first conductive layer; and
a second conductive layer,
the first piezoelectric layer being on the first conductive layer,
the second piezoelectric layer being on the first piezoelectric layer, and
the second conductive layer being connected to the conductive layer on the top surface of the gate dielectric layer.

3. The composite field effect transistor of claim 1 , wherein the negative-capacitance piezoelectric stack is on the top surface of the gate dielectric layer.

4. The composite field effect transistor of claim 1 , wherein the composite field effect transistor has a subthreshold swing of less than 60 mV per decade.

5. The composite field effect transistor of claim 1 , wherein a thickness of the first piezoelectric layer is between 10 nm and 100 nm and a thickness of the second piezoelectric layer is between 10 nm and 100 nm.

6. The composite field effect transistor of claim 1 , wherein:
the first piezoelectric layer is poled in a first direction, the first direction being within 20 degrees of a direction perpendicular to a top surface of the first piezoelectric layer, and
the second piezoelectric layer is poled in a second direction, the second direction being within 20 degrees of the first direction.

7. The composite field effect transistor of claim 1 , wherein the negative-capacitance piezoelectric stack has an effective relative dielectric constant less than −0.2.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hatcher Ryan M
• Rakshit Titash
• Kittl Jorge A
• Hong Joon Goo
• Palle Dharmendar

Classifications

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title