FeFET transistor

Patent metadata

Field	Value
Publication number	US-11043591-B2
Application number	US-201916437067-A
Country	US
Kind code	B2
Filing date	Jun 11, 2019
Priority date	Jun 15, 2018
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A ferroelectric field effect transistor includes a semiconductor substrate, with first and second source/drain regions being formed within the semiconductor substrate and being separated by a channel region. An interface layer is disposed on the channel region. A gate insulator layer is disposed on the interface layer. A ferroelectric layer is disposed on the gate insulator layer.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a first transistor and a second transistor on a semiconductor substrate;
wherein a gate of the first transistor comprises:
a first portion of an interface layer on the semiconductor substrate, wherein the interface layer comprises silicon oxynitride;
a first portion of a gate insulator layer on the interface layer;
a first ferroelectric layer on the first portion of the gate insulator layer; and
a first portion of a metal gate layer on the first ferroelectric layer; and

wherein a gate of the second transistor comprises:
a second portion of the interface layer on the semiconductor substrate;
a second portion of the gate insulator layer on the interface layer; and
a second portion of the metal gate layer on the second portion of the gate insulator layer.

2. The integrated circuit of claim 1 , wherein the gate insulator layer comprises hafnium oxide.

3. The integrated circuit of claim 1 , wherein the first ferroelectric layer comprises a material selected from the group consisting of hafnium oxide and zirconium oxide.

4. The integrated circuit of claim 1 , further comprising a first layer favoring nucleation of an orthorhombic crystal structure positioned between the first ferroelectric layer and the gate insulator layer.

5. The integrated circuit of claim 4 , wherein the first layer is made of one compound or of a combination of compounds selected from the group consisting of:
lanthanum, lanthanum oxides, germanium, germanium oxides, gadolinium, gadolinium oxides, strontium, strontium oxides, yttrium, yttrium oxides, aluminum, aluminum oxides, silicon, and silicon oxides.

6. The integrated circuit of claim 4 , further comprising a stack disposed on the first ferroelectric layer, the stack comprising at least one second layer favoring nucleation of an orthorhombic crystal structure and at least one second ferroelectric layer.

7. The integrated circuit of claim 1 , wherein the second transistor is a MOS-type transistor.

8. An integrated circuit, comprising:
a semiconductor substrate;
an interface layer on the semiconductor substrate, wherein the interface layer comprises silicon oxynitride;
a first transistor supported by said semiconductor substrate;
a second transistor supported by said semiconductor substrate;
wherein the first transistor includes a first ferroelectric layer insulated from a first channel region of the semiconductor substrate by a first portion of a gate insulator layer and a first portion of a gate layer on the first ferroelectric layer, wherein the first portion of the gate insulator layer is on the interface layer; and
wherein the second transistor includes a second portion of a gate layer on a second portion of the gate insulator layer extending over a second channel region of the semiconductor substrate, wherein the second portion of the gate insulator layer is on the interface layer.

9. The integrated circuit of claim 8 , wherein the gate insulator layer comprises hafnium oxide.

10. The integrated circuit of claim 8 , wherein the first ferroelectric layer comprises a material selected from the group consisting of hafnium oxide and zirconium oxide.

11. The integrated circuit of claim 8 , wherein the first transistor is a FeFET-type transistor and the second transistor is a MOS-type transistor.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Gros-Jean Mickael
• Ferrand Julien

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/033 Primary

  comprising ferroelectric layers · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title