Gate oxide for nanosheet transistor devices

Patent metadata

Field	Value
Publication number	US-11211474-B2
Application number	US-202016742295-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	Jan 14, 2020
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming a protective oxide layer on a semiconductor substrate, the semiconductor substrate including a first substrate segment and a second substrate segment;
removing the protective oxide layer from the first substrate segment;
subsequent to removing the protective oxide layer from the first substate segment, forming a first nanosheet stack on the first substrate segment of the semiconductor substrate, the first nanosheet stack comprising a plurality of alternating first sacrificial layers and first channel layers, the first sacrificial layers each defining a first sacrificial height;
removing the protective oxide layer from the second substrate segment;
forming a second nanosheet stack on the second substrate segment of the semiconductor substrate, the second nanosheet stack comprising a plurality of alternating second sacrificial layers and second channel layers, the second sacrificial layers each defining a second sacrificial height greater than the first sacrificial height of the first sacrificial layers;
removing the first and second sacrificial layers respectively from the first and second nanosheet stacks; and
depositing a metal gate over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

2. The method of claim 1 wherein the first nanosheet stack includes a first given number of first channel layers and the second nanosheet stack includes a second given number of second channel layers, the second given number being less than the first given number.

3. The method of claim 2 wherein the first nanosheet stack includes three of the first channel layers and the second nanosheet stack includes two of the second channel layers.

4. The method of claim 2 wherein the height of the second sacrificial layers ranges from about 125 percent to about 200 percent greater than the height of the first sacrificial layers.

5. The method of claim 2 wherein the first and second sacrificial layers comprise silicon germanium and the first and second channel layers comprise silicon.

6. The method of claim 2 including forming the first and second nanosheets stacks to be substantially equal in height.

7. The method of claim 1 wherein the first and second nanosheet transistor structures are each gate dielectric nanosheet transistor structures.

8. The method of claim 7 including depositing an oxide material over the second nanosheet stack prior to depositing the metal gate.

9. The method of claim 8 further including:
depositing the oxide material over the first nanosheet stack;
depositing a block mask over the second nanosheet stack; and
selectively removing the oxide material from the first nanosheet stack.

10. The method of claim 8 including:
forming dummy gates on each of the first and second nanosheet stacks; and
removing the dummy gates from each of the first and second nanosheet stacks prior to depositing the metal gate.

11. The method of claim 8 including forming a source region and a drain region about each of the first and second nanosheet stacks.

12. The method of claim 11 further including forming an additional protective oxide layer on the protective oxide layer, and thereafter removing the additional protective layer prior to forming the second nanosheet stack.

13. The method of claim 11 wherein the steps of removing the protective oxide layer comprises one or more etching processes.

14. The method of claim 8 wherein depositing the oxide material includes:
forming oxide layers on opposing surfaces of adjacent second channel layers of the second nanosheet stack, and
forming oxide layers extending between the adjacent second channel members.

15. A method for forming a semiconductor substrate, comprising:
forming a protective oxide layer on a semiconductor substrate, the semiconductor substrate including a first substrate segment and a second substrate segment;
removing the protective oxide layer from the first substrate segment;
subsequent to removing the protective oxide layer from the first substate segment, forming a first nanosheet stack on the first substrate segment of the semiconductor substrate, the first nanosheet stack comprising a plurality of alternating first sacrificial layers and first channel layers;
removing the protective oxide layer from the second substrate segment;
forming a second nanosheet stack on the second substrate segment of the semiconductor substrate, the second nanosheet stack comprising a plurality of alternating second sacrificial layers and second channel layers, a number of the second sacrificial layers being less than a number of first sacrificial layers of the first nanosheet stack;
removing the first and second sacrificial layers respectively from the first and second nanosheet stacks; and
depositing a metal gate over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures on the semiconductor substrate.

16. The method of claim 15 wherein forming the second nanosheet stack includes forming the second sacrificial layers to define a height greater than a height of the first sacrificial layers of the first nanosheet stack.

17. The method of claim 16 wherein the first and second sacrificial layers comprise silicon germanium and the first and second channel layers comprise silicon and wherein forming the first and the second nanosheet stacks include epitaxially growing each of the first and second sacrificial layers and the first and second channel layers.

18. The method of claim 17 wherein the height of the second sacrificial layers ranges from about 125 percent to about 200 percent greater than the height of the first sacrificial layers.

19. The method of claim 16 including depositing an oxide material over the second nanosheet stack prior to depositing the metal gate.

20. The method of claim 14 wherein depositing the metal gate causes portions of the metal to be disposed between the adjacent second channel layers and in contacting relation with one or more first, second, third or fourth oxide layers.

Assignees

• IBM

Inventors

• Siddiqui Shahab
• Watanabe Koji
• Adams Charlotte Dewan
• Zhao Kai
• Dechene Daniel James
• Krishnan Rishikesh

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title