Nanosheet transistors having different gate dielectric thicknesses on the same chip

Patent metadata

Field	Value
Publication number	US-9935014-B1
Application number	US-201715404469-A
Country	US
Kind code	B1
Filing date	Jan 12, 2017
Priority date	Jan 12, 2017
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a first nanosheet stack on a substrate, the first nanosheet stack comprising a first sacrificial layer between a first nanosheet and a second nanosheet;
forming a second nanosheet stack on the substrate, the second nanosheet stack comprising a first sacrificial layer between a first nanosheet and a second nanosheet;
doping the first nanosheet of the first nanosheet stack; and
concurrently removing the first sacrificial layer and the first nanosheet of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

2. The method of claim 1 further comprising:
forming a dielectric layer over a channel region of the first nanosheet stack.

3. The method of claim 2 further comprising:
forming a first gate over the dielectric layer in the channel region of the first nanosheet stack;
forming a second gate over a channel region of the second nanosheet stack; and
forming a first gate contact on the first gate and a second gate contact on the second gate.

4. The method of claim 1 , wherein the first and second nanosheet stacks each comprise a plurality of nanosheets alternating with a plurality of sacrificial layers such that each pair of adjacent nanosheets is separated by a sacrificial layer.

5. The method of claim 4 , wherein each nanosheet of the first and second nanosheet stacks has a thickness of about 4 nm to about 10 nm.

6. The method of claim 4 , wherein a thickness of the first sacrificial layer of the first nanosheet stack is at least twice a thickness of a second sacrificial layer of the first nanosheet stack.

7. The method of claim 1 , wherein the first and second nanosheet stacks are concurrently formed by removing portions of a semiconductor layer.

8. The method of claim 1 , wherein the first and second nanosheets of the first and second nanosheet stacks are Si nanosheets and each of the sacrificial layers of the first and second nanosheets stacks comprise SiGe.

9. The method of claim 1 , wherein doping the first nanosheet of the first nanosheet stack further comprises plasma doping the first nanosheet with a Ge dopant at a temperature of about 400 degrees Celsius to about 700 degrees Celsius.

10. A method for forming a semiconductor device, the method comprising:
forming a nanosheet stack on a substrate, the nanosheet stack comprising a first sacrificial layer between a first nanosheet and a second nanosheet;
doping a portion of the first nanosheet; and
concurrently removing the doped portion of the first nanosheet and the first sacrificial layer.

11. The method of claim 10 further comprising:
forming a gate over the channel region of the nano sheet stack; and
forming a gate contact on the gate.

12. The method of claim 10 , wherein the nanosheet stack further comprises a plurality of nanosheets alternating with a plurality of sacrificial layers such that each pair of adjacent nanosheets is separated by a sacrificial layer.

13. The method of claim 12 , wherein each nanosheet of the nanosheet stack has a thickness of about 4 nm to about 10 nm.

14. The method of claim 12 , wherein a thickness of the first sacrificial layer is at least twice a thickness of the second sacrificial layer.

15. The method of claim 10 , wherein the first and second nanosheets are Si nanosheets and the first and second sacrificial layers comprise SiGe.

16. The method of claim 10 , wherein doping a portion of the first nanosheet further comprises plasma doping the portion of the first nanosheet with a Ge dopant at a temperature of about 400 degrees Celsius to about 700 degrees Celsius.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L29/42392

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic

• H01L21/223

  Electricity · mapped topic