High voltage three-dimensional devices having dielectric liners

Patent metadata

Field	Value
Publication number	US-9972642-B2
Application number	US-201715784318-A
Country	US
Kind code	B2
Filing date	Oct 16, 2017
Priority date	Jun 28, 2012
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

First claim

What is claimed is:

1. A method, comprising:
forming a first transistor, wherein forming a first transistor comprises:
forming a first body having at least a top, a first sidewall, and a second sidewall opposite the first sidewall;
forming a first dummy gate structure on the first body;
forming spacers adjacent sidewalls of the first dummy gate structure;
removing the first dummy gate structure;
forming a first gate dielectric structure that covers the top and at least a portion of the first and second sidewalls of the first body, the first gate dielectric structure comprising a first dielectric layer of a first gate dielectric material and a second dielectric layer of a second gate dielectric material, the first dielectric structure having a first total thickness;
forming a first gate electrode structure that covers at least a portion of the first gate dielectric structure on the top and at least a portion of the first and second sidewalls of the first body; and
forming a first source region and a first drain region on opposite sides of the first gate electrode structure; and
forming a first source contact having a first minimum distance to the first gate electrode structure, the first minimum distance being the distance where the first source contact is closest to the first gate electrode structure; and

forming a second transistor, wherein forming the second transistor comprises:
forming a second body with at least a top, a first sidewall, and a second sidewall opposite the first sidewall;
forming a second dummy gate structure on the second body;
forming spacers adjacent sidewalls of the second dummy gate structure;
removing the second dummy gate structure;
forming a second gate dielectric structure that that covers the top and at least a portion of the first and second sidewalls of the second body, the second gate dielectric structure comprising a first dielectric layer of the first gate dielectric material, the second dielectric structure having a second total thickness smaller than the first total thickness of the first gate dielectric structure;
forming a second gate electrode structure that that covers at least a portion of the second gate dielectric structure on the top and at least a portion of the first and second sidewalls of the second body;
forming a second source region and a second drain region on opposite sides of the second gate electrode structure; and
forming a second source contact having a second minimum distance to the second gate electrode structure, the second minimum distance being the distance where the second source contact is closest to the second gate electrode structure, the second minimum distance being smaller than the first minimum distance.

2. The method of claim 1 , wherein the first transistor is more capable of tolerating higher voltages than the second transistor.

3. The method of claim 1 , wherein the first gate dielectric material comprises a high k value material.

4. The method of claim 3 , wherein the first gate dielectric material comprises hafnium and oxygen.

5. The method of claim 1 , wherein the second gate dielectric structure further comprises a second dielectric layer comprising a second gate dielectric material having a k value lower than a k value of the first gate dielectric material.

6. The method of claim 5 , wherein the second gate dielectric material comprises an oxide of a semiconductor material of which the second body is comprised, the second dielectric layer being between the first dielectric layer of the second gate dielectric structure and the second body.

7. The method of claim 5 , wherein the first dielectric layer of the first gate dielectric structure is in contact with the top portion and at least a portion of the first and second sidewalls of the first body.

8. A method of fabricating an integrated circuit structure, the method comprising:
forming a first transistor, the forming comprising:
forming a first semiconductor fin having a top portion, a first sidewall and a second sidewall, the first semiconductor fin comprising a semiconductor material;
forming a first gate dielectric structure directly on the top portion and at least a portion of the first sidewalls and at least a portion of the second sidewall of the first semiconductor fin, the first gate dielectric structure comprising a first dielectric layer that conforms to the top portion of the first semiconductor fin and to at least the portion of both the first sidewall and the portion of second sidewall of the first semiconductor fin, and a second dielectric layer, the second dielectric layer conforming to a top portion of the first dielectric layer and to at least a portion of the first dielectric layer that conforms to the first sidewall of the first semiconductor fin and to at least a portion of the first dielectric layer that conforms to the second sidewall of the first semiconductor fin, the first gate dielectric structure having a first total thickness that is substantially the same at the top of the first semiconductor fin and at a first location adjacent the first sidewall of the first semiconductor fin and at a second location adjacent the second sidewall of the first semiconductor fin;
forming a first gate electrode on the first gate dielectric structure, the first gate dielectric structure being between the first gate electrode and the top portion of the first semiconductor fin, at least a portion of the first sidewall of the first semiconductor fin, and at least a portion of the second sidewall of the first semiconductor fin; and
forming a first source contact, the first source contact being separated from the first gate electrode by a first distance; and

forming a second transistor, the forming comprising:
forming a second semiconductor fin having a top portion, a first sidewall and a second sidewall, the second semiconductor fin comprising a semiconductor material;
forming a second gate dielectric structure directly on the top portion and at least a portion of the first sidewalls and at least a portion of the second sidewall of the second semiconductor fin, the second gate dielectric structure comprising a first dielectric layer that conforms to the top portion of the second semiconductor fin and to at least the portion of both the first sidewall and the portion of the second sidewall of the second semiconductor fin, the second gate dielectric structure having a second total thickness that is substantially the same at the top of the second semiconductor fin and at a first location adjacent the first sidewall of the second semiconductor fin and at a second location adjacent the second sidewall of the second semiconductor fin, the second total thickness being smaller than the first total thickness;
forming a second gate electrode on the second gate dielectric structure, the second gate dielectric structure being between the second gate electrode and the top portion of the second semiconductor fin, at least a portion of the first sidewall of the second semiconductor fin, and at least a portion of the second sidewall of the second semiconductor fin; and
forming a second source contact, the second source contact being separated from the second gate electrode by a second distance smaller than the first distance.

9. The method of claim 8 , wherein the first transistor is more capable of tolerating higher voltages than the second transistor.

10. The method of claim 8 , wherein the second dielectric layer of the first gate dielectric structure comprises a high k value material.

11. The method of claim 10 , wherein the second dielectric layer of the first gate dielectric structure comprises hafnium and oxygen.

12. The met

Assignees

• Intel Corp

Inventors

• Hafez Walid M
• Yeh Jeng-Ya D
• Tsai Curtis
• Park Joodong
• Jan Chia-Hong
• Bhimarasetti Gopinath

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/01332

  Making the insulator · CPC title