Semiconductor device and method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-11211459-B2
Application number	US-201916715439-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Dec 17, 2018
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing an auxiliary carrier and a silicon carbide substrate, the silicon carbide substrate comprising an idle layer and a device layer, the device layer being located between the idle layer and a main surface of the silicon carbide substrate at a front side of the silicon carbide substrate, the device layer comprising a plurality of laterally separated device regions, each device region extending from the main surface to the idle layer, the auxiliary carrier being structurally connected with the silicon carbide substrate at the front side;
removing the idle layer;
forming a mold structure filling a grid-shaped groove that laterally separates the device regions;
separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the device regions;
forming backside metal structures selectively on a backside surface of the device regions; and
after removing the idle layer and prior to forming the mold structure, providing a preform that comprises laterally separated stencil portions,
wherein the stencil portions are provided on the backside surface of the device regions and each stencil portion is assigned to one device region,
wherein the mold structure fills a space between the stencil portions.

2. The method of claim 1 , wherein the grid-shaped groove is formed prior to removing the idle layer.

3. The method of claim 1 , wherein the grid-shaped groove is formed after removing the idle layer.

4. The method of claim 1 , further comprising:
prior to molding, redistributing the device regions such that at least one of the device regions is replaced with a supplementary device region obtained from a further semiconductor substrate.

5. The method of claim 1 , further comprising:
removing the preform after forming the mold structure.

6. The method of claim 5 , further comprising:
forming at least a portion of the backside metal structures in spaces left by removing the stencil portions.

7. The method of claim 6 , further comprising:
prior to applying the preform, forming a metal seed layer on the backside surface and on sidewalls of the device regions,
wherein forming the backside metal structures comprises electrochemical deposition of main metal portions on portions of the metal seed layer exposed in the spaces.

8. The method of claim 7 , wherein the metal seed layer comprises an access portion formed on the auxiliary carrier, wherein the mold structure is formed to expose the access portion, and wherein the auxiliary carrier is removed after forming the main metal portions.

9. The method of claim 1 , further comprising:
removing a layer portion of the mold structure formed outside the grid-shaped groove such that the backside surface of the laterally separated device regions is exposed.

10. The method of claim 9 , further comprising:
after removing the layer portion of the mold structure, forming a metal seed layer on the backside surface of the device regions; and
forming laterally separated main metal portions on the metal seed layer,
wherein forming the main metal portions comprises pattern plating.

11. The method of claim 1 , further comprising:
prior to structurally connecting the auxiliary carrier and the silicon carbide substrate, forming a front side metallization on the main surface of the silicon carbide substrate.

12. The method of claim 1 , wherein removing the idle layer comprises splitting of the idle layer from the device layer.

13. A method of manufacturing a semiconductor device, the method comprising:
providing an auxiliary carrier and a silicon carbide substrate, the silicon carbide substrate comprising an idle layer and a device layer, the device layer being located between the idle layer and a main surface of the silicon carbide substrate at a front side of the silicon carbide substrate, the device layer comprising a plurality of laterally separated device regions, each device region extending from the main surface to the idle layer, the auxiliary carrier being structurally connected with the silicon carbide substrate at the front side;
removing the idle layer;
forming a mold structure filling a grid-shaped groove that laterally separates the device regions;
removing a layer portion of the mold structure formed outside the grid-shaped groove such that a backside surface of the laterally separated device regions is exposed; and
separating the device regions,
wherein parts of the mold structure form frame structures laterally surrounding the device regions.

14. The method of claim 13 , further comprising:
after removing the layer portion of the mold structure, forming a metal seed layer on the backside surface of the device regions; and
forming laterally separated main metal portions on the metal seed layer,
wherein forming the main metal portions comprises pattern plating.

Assignees

• Infineon Technologies Ag

Inventors

• Brockmeier Andre
• Denifl Guenter
• Kern Ronny
• Knabl Michael
• Piccin Matteo
• Santos Rodriguez Francisco Javier

Classifications

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P14/2904

  Silicon carbide · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/016

  using moulds · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title