Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11211456-B2
Application number	US-202016751726-A
Country	US
Kind code	B2
Filing date	Jan 24, 2020
Priority date	May 17, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape;
a growth prevention pattern on the recess;
gate structures on portions of the active pattern at opposite sides of the recess;
channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and
a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels,
wherein a top surface of the growth prevention pattern is not higher than a bottom surface of the gate structures.

2. The semiconductor device of claim 1 , wherein the source/drain layer includes:
a first epitaxial layer on a sidewall of each of the channels; and
a second epitaxial layer on the growth prevention pattern, the second epitaxial layer adjacent to the first epitaxial layer.

3. The semiconductor device of claim 2 , wherein the source/drain layer includes silicon doped with n-type impurities or silicon carbide doped with n-type impurities, and
wherein an impurity concentration of the second epitaxial layer is greater than that of the first epitaxial layer.

4. The semiconductor device of claim 2 , wherein the first epitaxial layer has a shape of a candle or an ellipse protruding from the sidewall of each of the channels in a horizontal direction parallel to the tipper surface of the substrate.

5. The semiconductor device of claim 1 , wherein the source/drain layer includes:
a first epitaxial layer on a sidewall of each of the channels;
a second epitaxial layer protruding from the first epitaxial layer in a horizontal direction parallel to the upper surface of the substrate; and
a third epitaxial layer on the growth prevention pattern, the third epitaxial layer adjacent to the second epitaxial layer.

6. The semiconductor device of claim 5 , wherein the source/drain layer includes silicon-germanium doped with p-type impurities, and
wherein an impurity concentration of the third epitaxial layer is greater than an impurity concentration of the second epitaxial layer, and the impurity concentration of the second epitaxial layer is greater than an impurity concentration of the first epitaxial layer.

7. The semiconductor device of claim 6 , wherein a germanium concentration of the third epitaxial layer is greater than a germanium concentration of the second epitaxial layer, and the germanium concentration of the second epitaxial layer is greater than a germanium concentration of the first epitaxial layer.

8. The semiconductor device of claim 5 , wherein each of the first, second and third epitaxial layers includes silicon-germanium doped with p-type impurities, and wherein the source/drain layer further includes a fourth epitaxial layer on the third epitaxial layer, the fourth epitaxial layer including silicon.

9. The semiconductor device of claim 5 , wherein the second epitaxial layer has a shape of a pentagon protruding from the first epitaxial layer in a horizontal direction parallel to the upper surface of the substrate.

10. The semiconductor device of claim 1 , further comprising a first air gap between the growth prevention pattern and the source/drain layer.

11. The semiconductor device of claim 1 , further comprising an inner spacer on a sidewall of each of the gate structures between the channels, and a sidewall of each of the gate structures between an upper surface of the active pattern and a lowermost one of the channels.

12. The semiconductor device of claim 11 , wherein the inner spacer includes a material substantially the same as that of the growth prevention pattern.

13. The semiconductor device of claim 11 , further comprising a second air gap between the inner spacer and the source/drain layer.

14. The semiconductor device of claim 11 , wherein the inner spacer on the sidewall of the gate structures between the upper surface of the active pattern and the lowermost one of the channels contacts the growth prevention pattern.

15. The semiconductor device of claim 11 , wherein the inner spacer on the sidewall of the gate structures between the upper surface of the active pattern and the lowermost one of the channels is spaced apart from the growth prevention pattern.

16. A semiconductor device, comprising:
an active pattern on a substrate;
channels spaced apart from each other in a first direction perpendicular to a surface of the substrate;
a gate structure on the active pattern, the gate structure surrounding at least a portion of a surface of each of the channels; and
a source/drain layer on a portion of the active pattern at each of opposite sides of the gate structure and contacting the channels, the source/drain layer including a semiconductor material doped with n-type or p-type impurities and including:
a first epitaxial layer on a sidewall of each of the channels, the first epitaxial layer including a first impurity concentration; and
a second epitaxial layer on the active pattern, the second epitaxial layer surrounding the first epitaxial layers and having a second impurity concentration greater than the first impurity concentration,
wherein a growth prevention pattern is formed between the active pattern and the source/drain layer.

17. The semiconductor device of claim 16 , wherein the source/drain layer includes silicon doped with n-type impurities or silicon carbide doped with n-type impurities.

18. The semiconductor device of claim 17 , wherein the first epitaxial layer has a shape of a candle or an ellipse protruding from the sidewall of each of the channels in a second direction parallel to the surface of the substrate.

19. The semiconductor device of claim 16 , further comprising a first air gap between the growth prevention pattern and the source/drain layer.

20. A semiconductor device, comprising:
an active pattern on a substrate;
a gate structure on the active pattern;
channels spaced apart from each other in a direction perpendicular to an upper surface of the substrate, each of the channels disposed in the gate structure;
a blocking layer on a portion of the active pattern at each of opposite sides of the gate structure, the blocking layer not overlapping an uppermost surface of the active pattern;
a source/drain layer on the blocking layer, the source/drain layer being connected to the channels;
a spacer on a sidewall of a first portion of the gate structure between the channels and on sidewall of a second portion of the gate structure between an upper surface of the active pattern and a lowermost one of the channels; and
an air gap between the spacer and the source/drain layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Sujin
• Kim Kihwan
• Jang Sunguk
• Cho Youngdae

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title