Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11211308-B2
Application number	US-201916729504-A
Country	US
Kind code	B2
Filing date	Dec 30, 2019
Priority date	Mar 12, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a transistor and a heat dissipation structure. The substrate includes first and second semiconductor layers, and includes an insulating layer disposed between the first and second semiconductor layers. The substrate has a recess extending into the insulating layer from a surface of the first semiconductor layer. The transistor includes a hetero-junction structure, a gate electrode, a drain electrode and a source electrode. The hetero-junction structure is disposed on the second semiconductor layer. The gate, drain and source electrodes are disposed over the hetero-junction structure. The gate electrode is located between the drain electrode and the source electrode, and an active area of the hetero-junction structure located between the drain electrode and the source electrode is overlapped with the recess of the substrate. The heat dissipation structure is disposed on the surface of the first semiconductor layer, and extends into the recess.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate, comprising a first semiconductor layer, a second semiconductor layer and an insulating layer disposed between the first semiconductor layer and the second semiconductor layer, wherein the substrate has a recess, and the recess extends into the insulating layer from a surface of the first semiconductor layer, a recessed surface of the insulating layer defines a top surface of the recess, and a recessed portion of the insulating layer has a first thickness less than a second thickness of portions of the insulating layer aside the recess;
a transistor, comprising a hetero-junction structure, a gate electrode, a drain electrode and a source electrode, wherein the hetero-junction structure is disposed on the second semiconductor layer, the gate electrode, the drain electrode and the source electrode are disposed on the hetero-junction structure, the gate electrode is located between the drain electrode and the source electrode, and an active area of the hetero-junction structure between the drain electrode and the source electrode is overlapped with the recess of the substrate; and
a heat dissipation structure, disposed on the surface of the first semiconductor layer, and extending into the recess.

2. The semiconductor device according to claim 1 , wherein the recess is further overlapped with the drain electrode and the source electrode.

3. The semiconductor device according to claim 2 , wherein an area of an orthogonal projection of the recess on the second semiconductor layer is greater than or equal to an area of an orthogonal projection of the hetero-junction structure on the second semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the heat dissipation structure comprises a plurality of multilayer structures stacking on one another, each multilayer structure comprises an adhesive layer and a heat dissipation layer, and the adhesive layer is closer to the substrate than the heat dissipation layer in the same multilayer structure.

5. The semiconductor device according to claim 4 , wherein a ratio of a thickness of the heat dissipation layer with respect to a thickness of the adhesive layer ranges from 3:1 to 4:1.

6. The semiconductor device according to claim 4 , wherein an amount of the multilayer structures ranges from 4 to 6.

7. The semiconductor device according to claim 1 , wherein the hetero-junction structure comprises a channel layer, a spacer layer and a bather layer, wherein the channel layer is disposed between the second semiconductor layer of the substrate and the barrier layer, and the spacer layer s located between the channel layer and the barrier layer.

8. The semiconductor device according to claim 1 , wherein a ratio of the first thickness with respect to the second thickness ranges from 0.4 to 0.6.

9. A manufacturing method of a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first semiconductor layer, a second semiconductor layer and an insulating layer disposed between the first semiconductor layer and the second semiconductor layer;
forming a transistor on the second semiconductor layer of the substrate, wherein the transistor comprises a hetero-junction structure and a gate electrode, a drain electrode and a source electrode disposed on the hetero-junction structure, and the gate electrode is located between the drain electrode and the source electrode;
forming a recess at a surface of the substrate, wherein the recess extends into the insulating layer from a bottom surface of the first semiconductor layer, a recessed surface of the insulating layer defines a top surface of the recess, and a recessed portion of the insulating layer has a first thickness less than a second thickness of portions of the insulating layer aside the recess; and
forming a heat dissipation structure on the surface of the substrate, wherein the heat dissipation structure extends into the recess.

10. The manufacturing method of the semiconductor device according to claim 9 , further comprising thinning the first semiconductor layer before forming the recess.

Assignees

• Globalwafers Co Ltd

Inventors

• Chiu Hsien-Chin
• Shih Ying-Ru

Classifications

• H10W40/253

  Semiconductors · CPC title

• H10W40/70

  Fillings or auxiliary members in containers or in encapsulations for thermal protection or control · CPC title

• H10W40/22 Primary

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W40/255 Primary

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W40/254

  Diamond · CPC title