High dielectric constant material at locations of high fields

US11205696B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11205696-B2
Application numberUS-201916726477-A
CountryUS
Kind codeB2
Filing dateDec 24, 2019
Priority dateDec 24, 2019
Publication dateDec 21, 2021
Grant dateDec 21, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit comprising: a bottom conductive plate above a substrate; a first dielectric layer above the bottom conductive plate, the first dielectric layer formed of a first dielectric material; a top conductive plate above a first portion of the first dielectric material; and a ring structure formed of at least a second dielectric material having a higher dielectric constant than the first dielectric material, an inner perimeter of the ring structure being below a portion of the top conductive plate and an outer perimeter of the ring structure being outside an edge of the top conductive plate. 2. The integrated circuit as recited in claim 1 wherein the inner perimeter of the ring structure is laterally adjacent to a portion of the top conductive plate and the outer perimeter of the ring structure is laterally adjacent to a second portion of the first dielectric layer. 3. The integrated circuit as recited in claim 1 wherein the inner perimeter of the ring structure is laterally adjacent to a top region of the first dielectric material underneath the top conductive plate and the outer perimeter of the ring structure is laterally adjacent to a second portion of the first dielectric layer. 4. The integrated circuit as recited in claim 1 wherein the ring structure includes a layer formed of silicon nitride or aluminum oxide. 5. The integrated circuit as recited in claim 1 wherein the bottom conductive plate is smaller than the top conductive plate and an outer edge of the bottom conductive plate extends no further than the inner perimeter of the ring structure. 6. The integrated circuit as recited in claim 1 further comprising a bond wire attached to a top surface of the top conductive plate and positioned on the top surface of the top conductive plate above a portion of a bottom surface of the top conductive plate that is adjacent to the first portion of the first dielectric layer. 7. The integrated circuit as recited in claim 1 further comprising: a second ring structure formed of the second dielectric material having a second inner perimeter and a second outer perimeter, the second inner perimeter of the second ring structure being above a portion of the bottom conductive plate; and wherein an edge of the bottom conductive plate is adjacent to a portion of a bottom surface of the ring structure between the second inner perimeter of the second ring structure and the second outer perimeter of the second ring structure. 8. The integrated circuit as recited in claim 1 wherein a width of the ring structure is between 5 and 40 microns. 9. The integrated circuit as recited in claim 1 wherein each layer of the ring structure has a thickness of less than 1.2 microns. 10. A method of making an integrated circuit comprising: forming a bottom conductive plate above a substrate; forming a first dielectric layer of a first dielectric material above the bottom conductive plate; forming a ring structure of at least a second dielectric material having a higher dielectric constant than the first dielectric material, the ring structure being formed above a first portion of the first dielectric layer, the ring structure being formed with an inner perimeter and an outer perimeter; and forming a top conductive plate such that the inner perimeter of the ring structure is under a first portion of the top conductive plate and a portion of a top surface of the ring structure is adjacent to the first portion of the top conductive plate and the outer perimeter of the ring structure extends beyond an edge of the top conductive plate. 11. The method as recited in claim 10 further comprising forming the top conductive plate above the first dielectric layer. 12. The method as recited in claim 10 further comprising forming the top conductive plate such that a bottom surface of the top conductive plate is above the ring structure. 13. The method as recited in claim 12 further comprising: forming the inner perimeter of the ring structure to be laterally adjacent to a top region of the first dielectric layer underneath the top conductive plate; and forming the outer perimeter of the ring structure to be laterally adjacent to a second portion of the first dielectric layer. 14. The method as recited in claim 10 further comprising forming the inner perimeter of the ring structure to be laterally adjacent to a portion of the top conductive plate and the outer perimeter laterally adjacent to a second portion of the first dielectric layer. 15. The method as recited in claim 14 further comprising: forming a layer of the second dielectric material above the first dielectric layer; removing a first portion of the layer of the second dielectric material to form the ring structure; and forming the top conductive plate with a portion of the top conductive plate being formed in a region where the first portion of the layer was removed. 16. The method as recited in claim 10 further comprising forming the ring structure of silicon nitride or aluminum oxide. 17. The method as recited in claim 10 further comprising forming the bottom conductive plate to be smaller than the top conductive plate such that an edge of the bottom conductive plate extends no farther than the inside perimeter of the ring structure. 18. The method as recited in claim 10 further comprising attaching a bond wire to a top surface of the top conductive plate, the bond wire being attached to the top surface above a portion of a bottom surface of the top conductive plate that is above and adjacent to the first portion of the first dielectric layer. 19. The method as recited in claim 10 further comprising: forming a second ring structure of the second dielectric material, the second ring structure having a second inner perimeter and a second outer perimeter, the second inner perimeter of the second ring structure being above a portion of the bottom conductive plate; and wherein an edge of the bottom conductive plate is adjacent to a portion of a bottom surface of the second ring structure between the second inner perimeter of the second ring structure and the second outer perimeter of the second ring structure. 20. The method as recited in claim 10 further comprising forming the ring structure with a width of between 5 and 40 microns and forming each layer of the ring structure with a thickness of less than 1.2 microns. 21. The method as recited in claim 10 further comprising forming the ring structure with more than one dielectric material.

Assignees

Inventors

Classifications

  • Materials of bond wires · CPC title

  • the connected ends being ball-shaped · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Bond pads specially adapted therefor · CPC title

  • Reinforcing structures, e.g. collars · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11205696B2 cover?
An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also …
Who is the assignee on this patent?
Silicon Lab Inc, Skyworks Solutions Inc
What technology area does this patent fall under?
Primary CPC classification H10D1/692. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 21 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).