Memory arrays and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-11205654-B2
Application number	US-201916550238-A
Country	US
Kind code	B2
Filing date	Aug 25, 2019
Priority date	Aug 25, 2019
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

First claim

The invention claimed is:

1. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, the memory blocks being longitudinally elongated along a horizontal direction, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings being arranged horizontally along lateral rows that are orthogonal to the horizontal direction; and
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising longitudinally-alternating first and second regions individually having a vertically-elongated seam therein, the first regions being laterally-between the memory blocks between longitudinally-adjacent of the lateral rows and not being in the longitudinally-adjacent lateral rows, the second regions being laterally-between the memory blocks in the longitudinally-adjacent lateral rows and not being between the longitudinally-adjacent lateral rows, the vertically-elongated seam in the first regions being taller than in the second regions.

2. The memory array of claim 1 wherein the vertically-elongated seams in the first regions have higher tops than in the second regions.

3. The memory array of claim 1 wherein the intervening material comprises a laterally-outermost insulative material and a laterally-inner material of different composition from that of the laterally-outermost insulative material, the vertically-elongated seams in the first and second regions being in the laterally-inner material.

4. The memory array of claim 3 wherein the laterally-outermost insulative material comprises silicon dioxide and the laterally-inner material comprises undoped polysilicon.

5. The memory array of claim 1 wherein the intervening material is everywhere insulative between the immediately-laterally-adjacent memory blocks.

6. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising longitudinally-alternating first and second regions individually having a vertically-elongated seam therein, the vertically-elongated seam in the first regions being taller than in the second regions; and
the vertically-elongated seams in the first regions individually comprise at least one void space and the vertically-elongated seams in the second regions individually comprise at least one void space.

7. The memory array of claim 6 wherein the vertically-elongated seams in the first and second regions individually comprise multiple vertically-spaced void spaces, the vertically-elongated seams including portions thereof that extend vertically-between and connect with immediately-vertically-adjacent of the vertically-spaced void spaces.

8. The memory array of claim 6 wherein the vertically-elongated seams in the first and second regions individually comprise only one void space.

9. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, the memory blocks being longitudinally elongated along a horizontal direction, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings being arranged horizontally along lateral rows that are orthogonal to the horizontal direction; and
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising longitudinally-alternating first and second regions individually having a vertically-elongated seam therein, the first regions being laterally-between the memory blocks between longitudinally-adjacent of the lateral rows and not being in the longitudinally-adjacent lateral rows, the second regions being laterally-between the memory blocks in the longitudinally-adjacent lateral rows and not being between the longitudinally-adjacent lateral rows, the vertically-elongated seam in the first regions having a higher top than in the second regions.

10. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising longitudinally-alternating first and second regions individually having a vertically-elongated seam therein, the vertically-elongated seam in the first regions having a higher top than in the second regions; and
the vertically-elongated seams in the first regions individually comprise at least one void space and the vertically-elongated seams in the second regions individually comprise at least one void space.

11. The memory array of claim 10 wherein the vertically-elongated seams in the first and second regions individually comprise multiple vertically-spaced void spaces, the vertically-elongated seams including portions thereof that extend vertically-between and connect with immediately-vertically-adjacent of the vertically-spaced void spaces.

12. The memory array of claim 10 wherein the vertically-elongated seams in the first and second regions individually comprise only one void space.

13. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, the memory blocks being longitudinally elongated along a horizontal direction, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the operative channel-material strings being arranged horizontally along lateral rows that are orthogonal to the horizontal direction;
insulating bridges atop the stack extending laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks; and
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks and directly under the insulating bridges, the intervening material comprising longitudinally-alternating first and second regions, the first regions being laterally-between the memory blocks between longitudinally-adjacent of the lateral rows and not being in the longitudinally-adjacent lateral rows, the second regions being laterally-between the memory blocks in the longitudinally-adjacent lateral rows and not being between the longitudinally-adjacent lateral rows, the bridges not being directly above the intervening material in the second regions.

14. The memory array of claim 13 wherein insulative material of the bridges is directly against and of the same composition as insulative material of a top insulative tier of the stack.

15. The memory array of claim 13 wherein insulative material of the bridges is of different composition

Assignees

• Micron Technology Inc

Inventors

• Hu Yi
• Abdelrahaman Ramey M
• Bilik Narula
• Billingsley Daniel
• Bo Zhenyu
• Kash Joan M
• King Matthew J
• Li Andrew
• Neumeyer David
• Ng Wei Yeeng
• Pak Yung K
• Tiwari Chandra
• Wang Yiping
• Williamson Lance
• Zhang Xiaosong

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title