Non-volatile memory device and control method

Patent metadata

Field	Value
Publication number	US-11205494-B2
Application number	US-202117179356-A
Country	US
Kind code	B2
Filing date	Feb 18, 2021
Priority date	Oct 31, 2019
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array comprising memory strings, each memory string comprising a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells;
a plurality of word lines respectively coupled to the top memory cells and the bottom memory cells;
one or more dummy word lines respectively coupled to the one or more dummy memory cells; and
a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines, wherein, to program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period, wherein the biased dummy word line pre-pulse signal is a negative voltage signal.

2. The memory device of claim 1 , wherein
the control circuit is configured to program in a direction from the bottom memory cells to the top memory cells; and
the target memory cell is one of the top memory cells.

3. The memory device of claim 1 , further comprising a bit line coupled to an unselected memory string of the memory strings, wherein, to program the target memory cell, the control circuit is further configured to apply a biased bit line pre-pulse signal to the bit line in the pre-charge period.

4. The memory device of claim 3 , wherein the target memory cell is in a selected memory string of the memory strings different from the unselected memory string.

5. The memory device of claim 3 , wherein the biased bit line pre-pulse signal is a positive voltage signal.

6. The memory device of claim 3 , wherein, to program the target memory cell, the control circuit is further configured to:
apply a selected word line signal to the selected word line in the pre-charge period; and
apply an unselected word line signal to unselected word lines of the plurality of word lines in the pre-charge period.

7. The memory device of claim 6 , wherein the selected word line signal and the unselected word line signal each is a ground voltage.

8. The memory device of claim 3 , wherein
the unselected memory string further comprises a top select gate (TSG) transistor between the bit line and the top memory cells; and
to program the target memory cell, the control circuit is further configured to apply a biased TSG pre-pulse signal to the TSG transistor in the pre-charge period.

9. The memory device of claim 8 , wherein the biased TSG pre-pulse signal is a positive voltage signal.

10. A method for programming a memory device, the memory device comprising memory strings, each memory string comprising a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells, the method comprising:
programming a target memory cell coupled to a selected word line of a plurality of word lines, the plurality of word lines being respectively coupled to the top memory cells and the bottom memory cells,
wherein programming the target memory cell comprises applying a biased dummy word line pre-pulse signal to one or more dummy word lines in a pre-charge period prior to a programming period, the one or more dummy word lines being respectively coupled to the one or more dummy memory cells, wherein the biased dummy word line pre-pulse signal is a negative voltage signal.

11. The method of claim 10 , wherein
the memory device is programmed in a direction from the bottom memory cells to the top memory cells; and
the target memory cell is one of the top memory cells.

12. The method of claim 10 , wherein
the memory device further comprises a bit line coupled to an unselected memory string of the memory strings; and
programming the target memory cell further comprises applying a biased bit line pre-pulse signal to the bit line in the pre-charge period.

13. The method of claim 12 , wherein the target memory cell is in a selected memory string of the memory strings different from the unselected memory string.

14. The method of claim 12 , wherein the biased bit line pre-pulse signal is a positive voltage signal.

15. The method of claim 12 , wherein programming the target memory cell further comprises:
applying a selected word line signal to the selected word line in the pre-charge period; and
applying an unselected word line signal to unselected word lines of the plurality of word lines in the pre-charge period.

16. The method of claim 15 , wherein the selected word line signal and the unselected word line signal each is a ground voltage.

17. The method of claim 12 , wherein
the unselected memory string further comprises a top select gate (TSG) transistor between the bit line and the top memory cells; and
programming the target memory cell further comprises applying a biased TSG pre-pulse signal to the TSG transistor in the pre-charge period.

18. The method of claim 17 , wherein the biased TSG pre-pulse signal is a positive voltage signal.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Jia Jianquan
• You Kaikai
• Cui Ying
• Li Kaiwei
• Song Yali
• Li Shan
• Zhang An

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3431

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title