Operation method of non-volatile memory cell and applications thereof

Patent metadata

Field	Value
Publication number	US-9830992-B1
Application number	US-201615362052-A
Country	US
Kind code	B1
Filing date	Nov 28, 2016
Priority date	Jul 18, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

An operation method of a memory cell includes steps of applying a pre pulse before a read pulse is applied, wherein the pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage.

First claim

What is claimed is:

1. An operation method of a non-volatile memory cell, comprising:
applying a programming pulse to the non-volatile memory cell; and
applying a first pre pulse to the non-volatile memory cell before a read pulse is applied, wherein the first pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage of the non-volatile memory cell and has a conductivity opposite to that of the programming pulse.

2. The operation method according to claim 1 , wherein the read pulse is a programming verifying pulse.

3. The operation method according to claim 2 , wherein the programming verifying pulse comprise a first programming verifying level and a multi-level cell (MLC) programming verifying level.

4. The operation method according to claim 1 , wherein the programming pulse ranges from 16V to 20V.

5. The operation method according to claim 1 , wherein the first pre-pulse is less than the lowest threshold voltage and ranges from −5V to −6V.

6. The operation method according to claim 1 , further comprising steps of applying an erasing pulse to the non-volatile memory cell after applying the programming pulse.

7. The operation method according to claim 6 , further comprising:
applying a second pre-pulse to the non-volatile memory cell after applying the erasing pulse; and
applying an erasing verifying pulse to the non-volatile memory cell.

8. The operation method according to claim 7 , wherein the erasing verifying pulse comprises an erase level.

9. The operation method according to claim 1 , wherein the erasing pulse is −18V.

10. The operation method according to claim 7 , wherein the second pre-pulse is larger than the maximum threshold voltage and ranges from 2V to 8V.

11. A operation method of a non-volatile memory cell, comprising;
performing a programming operation comprising a first pre pulse before a programming verifying pulse and after a programming pulse on the non-volatile memory cell, wherein the first pre pulse and the programming pulse have opposite conductivities;
performing an erasing operation comprising a second pre pulse before an erasing verifying pulse and after an erasing pulse on the non-volatile memory cell; and
performing a reading operation comprising a third pre pulse before a read pulse on the non-volatile memory cell.

12. The operation method according to claim 11 , wherein the first pre pulse is a programming verifying pre pulse, the second pre pulse is an erasing verifying pre pulse and the third pre pulse is a reading pre pulse.

13. The operation method according to claim 11 , wherein the first pre-pulse is less than a lowest threshold voltage of the non-volatile memory cell and ranges from −5V to −6V.

14. The operation method according to claim 11 , wherein the second pre-pulse is larger than a maximum threshold voltage of the non-volatile memory cell and ranges from 2V to 8V.

15. The operation method according to claim 11 , wherein the third pre-pulse is larger than a maximum threshold voltage and ranges from 6V to 8V.

16. A circuitry for performing an operation of a non-volatile memory cell comprising;
a programming circuit for performing a programming operation comprising a first pre pulse before a programming verifying pulse and after a programming pulse on the non-volatile memory cell, wherein the first pre pulse and the programming pulse have opposite conductivities;
an erasing circuit for performing a erasing operation comprising a second pre pulse before an erasing verifying pulse and after a erasing pulse on the non-volatile memory cell; and
a reading circuit for performing a reading operation comprising a third pre pulse before a read pulse on the non-volatile memory cell.

17. The circuitry according to claim 16 , wherein the first pre pulse is a programming verifying pre pulse, the second pre pulse is an erasing verifying pre pulse and the third pre pulse is a reading pre pulse.

18. The circuitry according to claim 16 , wherein the first pre-pulse is less than a lowest threshold voltage of the non-volatile memory cell and ranges from −5V to −6V.

19. The circuitry according to claim 16 , wherein the second pre-pulse is larger than a maximum threshold voltage of the non-volatile memory cell and ranges from 2V to 8V.

20. The circuitry according to claim 16 , wherein the third pre-pulse is larger than a maximum threshold voltage of the non-volatile memory cell and ranges from 6V to 8V.

Assignees

• Macronix Int Co Ltd

Inventors

• Tsai Wen-Jer
• Lin Wei-Liang
• Cheng Chih-Chieh

Classifications

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title