Separate drain-side dummy word lines within a block to reduce program disturb

Patent metadata

Field	Value
Publication number	US-10297330-B2
Application number	US-201715615972-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Jun 7, 2017
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of conductive layers which are vertically spaced apart from one another by dielectric layers in a vertical stack of conductive layers, the plurality of conductive layers comprising a set of data word line layers, a set of dummy word line layers above the set of data word line layers, and a set of select gate layers above the set of dummy word line layers;
the set of dummy word line layers comprises a second dummy word line layer stacked above a first dummy word line layer in the stack, wherein the first dummy word line layer comprises a first set of separate conductive dummy word line layer portions that are not electrically connected to one another, and the second dummy word line layer comprises a second set of separate conductive dummy word line layer portions that are not electrically connected to one another;
the set of select gate layers includes a select gate layer comprising separate conductive select gate layer portions that are not electrically connected to one another, and are arranged, respectively, above the separate conductive dummy word line layer portions of the second set of separate conductive dummy word line layer portions of the second dummy word line layer; and
a plurality of memory cells surrounded by the vertical stack of conductive layers and arranged in a plurality of sub-blocks, the plurality of memory cells comprise data memory cells electrically connected to the set of data word line layers, first dummy memory cells electrically connected to the first set of separate conductive dummy word line layer portions of the first dummy word line layer, and second dummy memory cells electrically connected to the second set of separate conductive dummy word line layer portions of the second dummy word line layer, wherein each conductive dummy word line layer portion of the second set of separate conductive dummy word line layer portions of the second dummy word line layer corresponds to a respective sub-block of the plurality of sub-blocks, and each dummy word line layer portion of the first set of separate conductive dummy word line layer portions of the first dummy word line layer is shared among sub-blocks of the plurality of sub-blocks.

2. The memory device of claim 1 , further comprising select gate transistors connected to the separate conductive select gate layer portions, wherein:
the data memory cells are arranged in lower pillars;
the dummy memory cells and the select gate transistors are arranged in upper pillars above each of the lower pillars; and
a width at a top of each of the upper pillars is less than a width at a top of each of the lower pillars.

3. The memory device of claim 2 , wherein:
each pillar of the upper pillars and the lower pillars is tapered and is narrower at a bottom than at a top.

4. The memory device of claim 2 , wherein:
an isolation region separates one row of the upper pillars in one of the sub-blocks from another, adjacent row of the upper pillars in another of the sub-blocks;
one row of the upper pillars overlaps one row of the lower pillars and is offset from the one row of the lower pillars in a direction moving away from the isolation region; and
another row of the upper pillars which is adjacent to the one row of the upper pillars overlaps another row of the lower pillars and is offset from the another row of the lower pillars in a direction moving away from the isolation region.

5. The memory device of claim 4 , wherein:
the isolation region overlaps the lower pillars in the one row of the lower pillars and the lower pillars in the another row of the lower pillars.

6. The memory device of claim 1 , wherein:
the second set of separate conductive dummy word line layer portions comprise N separate conductive dummy word line layer portions; and
the first set of separate conductive dummy word line layer portions comprises two or more but fewer than N separate conductive dummy word line layer portions.

7. The memory device of claim 1 , further comprising:
circuitry configured to provide a voltage on a selected data word line layer in the set of data word line layers, and to apply a voltage on a selected dummy word line layer portion of the second set of separate conductive dummy word line layer portions of the second dummy word line layer which is higher than a voltage on unselected dummy word line layer portions of the second set of separate conductive dummy word line layer portions of the second dummy word line layer.

8. The memory device of claim 7 , wherein:
the voltage on the selected data word line layer comprises a program voltage; and
the voltage the unselected dummy word line layer portions is a function of a magnitude of the program voltage.

9. The memory device of claim 1 , wherein:
a ramp up rate of a voltage on a dummy word line layer portion of the second set of separate conductive dummy word line layer portions of the second dummy word line layer in a selected sub-block of the plurality of sub-blocks is different than a ramp up rate of a voltage on dummy word line layer portions of the second set of separate conductive dummy word line layer portions of the second dummy word line layer in of unselected sub-blocks of the plurality of sub-blocks.

10. A method, comprising:
applying a voltage to a selected data word line layer, wherein:
the selected data word line layer is among a plurality of data word line layers, which are among a vertical stack of a plurality of conductive layers that are vertically spaced apart from one another by dielectric layers;
the plurality of conductive layers comprise a set of dummy word line layers above the plurality of data word line layers, and a set of select gate layers above the set of dummy word line layers;
the set of dummy word line layers includes a second dummy word line layer stacked above a first dummy word line layer, wherein the second dummy word line layer comprises separate conductive dummy word line layer portions that are not electrically connected to one another;
the set of select gate layers includes a select gate layer comprising separate conductive select gate layer portions that are not electrically connected to one another, and are arranged, respectively, above the separate conductive dummy word line layer portions of the second dummy word line layer; and
a plurality of memory cells surrounded by the vertical stack of conductive layers and arranged in a plurality of sub-blocks, the plurality of memory cells comprise data memory cells electrically connected to the set of data word line layers, first dummy memory cells electrically connected to the first dummy word line layer, and second dummy memory cells electrically connected to the separate conductive dummy word line layer portions of the second dummy word line layer, wherein each of the separate conductive dummy word line layer portions of the second dummy word line layer corresponds to a respective sub-block of the plurality of sub-blocks; and

during the applying of the voltage to the selected data word line layer, applying a voltage on a selected dummy word line layer portion of the separate conductive dummy word line layer portions of the second dummy word line layer which is higher than a voltage applied to unselected dummy word line layer portions of the separate conductive dummy word line layer portions of the second dummy word line layer, wherein the voltage applied to the selected data word line layer comprises a program voltage and the voltage on the unselected dummy word line layer portions is a function of a magnitude of the program voltage.

11. The method of claim 10 , wherein:
the separate conductive dummy word line layer

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Zhengyi
• Chin Henry
• Dong Yingda

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• H01L27/11582

  Electricity · mapped topic

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title