Source driving circuit, driving method and display device

Patent metadata

Field	Value
Publication number	US-11205372-B2
Application number	US-201916960574-A
Country	US
Kind code	B2
Filing date	Sep 23, 2019
Priority date	Sep 23, 2019
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A source driving circuit includes a buffer amplifier configured to generate a driving signal from an original driving signal. The buffer amplifier includes a first amplifier and a second amplifier. A high-level terminal of the first amplifier is coupled to the first power signal terminal, a low-level terminal is coupled to the second power signal terminal, and an output terminal is configured to output a positive polarity driving signal. A high-level terminal of the second amplifier is coupled to the third power signal terminal, a low-level terminal is coupled to the fourth power signal terminal, and an output terminal is configured to output a negative polarity driving signal. The voltage of the second power signal terminal is less than the voltage of the third power signal terminal.

First claim

What is claimed is:

1. A source driving circuit, comprising a buffer amplifier configured to generate a driving signal from an original driving signal, wherein the buffer amplifier comprises:
a switching assembly;
a first amplifier having a high-level terminal coupled to a first power signal terminal, a low-level terminal coupled to a second power signal terminal or a fifth power signal terminal through the switching assembly, and an output terminal configured to output a positive polarity driving signal; and
a second amplifier having a high-level terminal coupled to a third power signal terminal or the fifth power signal terminal through the switching assembly, a low-level terminal coupled to a fourth power signal terminal, and an output terminal configured to output a negative polarity driving signal, wherein a voltage of the second power signal terminal is less than a voltage of the third power signal terminal, and the switching assembly is configured to:
connect the low-level terminal of the first amplifier with the second power signal terminal and connect the high-level terminal of the second amplifier with the third power signal terminal in a first driving state; and
connect the low-level terminal of the first amplifier with the fifth power signal terminal and connect the high-level terminal of the second amplifier with the fifth power signal terminal in a second driving state,

wherein the source driving circuit further comprises:
a detection circuit configured to detect a potential of an effective pulse signal for each row in the original driving signal in real time;
an arithmetic circuit coupled to the detection circuit, and configured to calculate a potential difference between the effective pulse signal for a current row and the effective pulse signal for a previous row in real time based on the potential of the effective pulse signal for each row; and
a control circuit coupled to the arithmetic circuit and the switching assembly, and configured to send a control signal to the switching assembly based on the potential difference between the effective pulse signal for the current row and the effective pulse signal for the previous row to control a driving state of the switching assembly, wherein:
when the potential difference between the effective pulse signal for the current row and the effective pulse signal for the previous row is greater than a preset value, the switching assembly is controlled to operate in the first driving state during at least a portion of a period of the current row; and
when the potential difference between the effective pulse signal for the current row and the effective pulse signal for the previous row is less than or equal to the preset value, the switching assembly is controlled to operate in the second driving state during a driving period of the current row.

2. The source driving circuit according to claim 1 , wherein:
a voltage of the first power signal terminal is a voltage of an analog power signal;
a voltage of the fourth power signal terminal is a ground voltage;
the voltage of the second power signal terminal is less than a voltage of a half-value analog power signal; and
the voltage of the third power signal terminal is greater than the voltage of the half-value analog power signal.

3. The source driving circuit according to claim 1 , wherein a voltage of the fifth power signal terminal is equal to the voltage of a half-value analog power signal.

4. The source driving circuit according to claim 1 , wherein the switching assembly comprises:
a first switching unit coupled to the low-level terminal of the first amplifier, the second power signal terminal, and a first control terminal, and configured to connect the low-level terminal of the first amplifier with the second power signal terminal in response to a signal of the first control terminal;
a second switching unit coupled to the high-level terminal of the second amplifier, the third power signal terminal, and the first control terminal, and configured to connect the high-level terminal of the second amplifier with the third power signal terminal in response to the signal of the first control terminal;
a third switching unit coupled to the low-level terminal of the first amplifier, the fifth power signal terminal, and a second control terminal, and configured to connect the low-level terminal of the first amplifier with the fifth power signal terminal in response to a signal of the second control terminal; and
a fourth switching unit coupled to the high-level terminal of the second amplifier, the fifth power signal terminal, and the second control terminal, and configured to connect the high-level terminal of the second amplifier with the fifth power signal terminal in response to the signal of the second control terminal.

5. The source driving circuit according to claim 4 , wherein:
the first switching unit comprises a first switching transistor having a first terminal coupled to the low-level terminal of the first amplifier, a second terminal coupled to the second power signal terminal, and a control terminal coupled to the first control terminal;
the second switching unit comprises a second switching transistor having a first terminal coupled to the high-level terminal of the second amplifier, a second terminal coupled to the third power signal terminal, and a control terminal coupled to the first control terminal;
the third switching unit comprises a third switching transistor having a first terminal coupled to the low-level terminal of the first amplifier, a second terminal coupled to the fifth power signal terminal, and a control terminal coupled to the second control terminal; and
the fourth switching unit comprises a fourth switching transistor having a first terminal coupled to the high-level terminal of the second amplifier, a second terminal coupled to the fifth power signal terminal, and a control terminal coupled to the second control terminal.

6. The source driving circuit according to claim 5 , wherein the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are N-type transistors or P-type transistors.

7. A driving method for a source driving circuit, comprising:
providing the source driving circuit, wherein the source driving circuit comprises:
a buffer amplifier configured to generate a driving signal from an original driving signal, wherein the buffer amplifier comprises a switching assembly;
a first amplifier having a high-level terminal coupled to a first power signal terminal, a low-level terminal coupled to a second power signal terminal or a fifth power signal terminal through the switching assembly, and an output terminal configured to output a positive polarity driving signal;
a second amplifier having a high-level terminal coupled to a third power signal terminal or the fifth power signal terminal through the switching assembly, a low-level terminal coupled to a fourth power signal terminal, and an output terminal configured to output a negative polarity driving signal, wherein a voltage of the second power signal terminal is less than a voltage of the third power signal terminal, and wherein the switching assembly is configured to: connect the low-level terminal of the first amplifier with the second power signal terminal and connect the high-level terminal of the second amplifier with the third power signal terminal in a first driving state; and connect the low-level terminal of the first amplifier with the fifth power signal terminal and connect the high-level terminal of the second amplifier with the fifth power signal terminal in a second driving state; and
a detection circuit, an arithmetic circuit, and a control circuit;

outputting the posit

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yang Yan
• Hung Chinghua
• Liu Rui
• Sun Wei
• Chen Ming
• Gu Qibing
• Chen Xiangyi

Classifications

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2320/0252

  Improving the response speed · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title