Data driver and display device driving method

Patent metadata

Field	Value
Publication number	US-9558698-B2
Application number	US-201414566672-A
Country	US
Kind code	B2
Filing date	Dec 10, 2014
Priority date	Apr 8, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A driving method for driving a display apparatus including a plurality of pixels, a plurality of data lines and a data driver. The data driver includes a first latch outputting a first sample data signal to a second latch, the second latch, a first charge sharing line and a second charge sharing line. The method includes performing a first charge sharing when a polarity of one of the pixels changes so as to output a first calibrated data signal to the data line electrically coupled to the pixel, and executing a second charge sharing when the most significant bit of the first sample data signal is different from the most significant bit of the second sample data signal so as to output a second adjusted data signal to the data line.

First claim

What is claimed is:

1. An electric charge share device, electrically connected to a data driver and a data line, comprising:
a data detection unit configured to determine if a most-significant-bit of a first sample data signal from the data driver is identical to a most-significant-bit of a second sample data signal from the data driver;
a first charge share line;
a second charge share line; and
a data signal charge share unit configured to receive a data signal from the data driver, electrically connected to the data detection unit, the first charge share line and the second charge share line, and comprising:
a first switch comprising:
a first terminal coupled to the first charge share line;
a second terminal coupled to the data line; and
a control terminal;

a second switch comprising:
a first terminal coupled to the second charge share line;
a second terminal coupled to the data line; and
a control terminal;

a first logic unit, coupled to the control terminal of the first switch; configured to control if the first switch is turned on according to whether a polarity of the data line changes, the polarity of the data line, and whether a difference between the first sample data signal and the second sample data signal is larger than a predetermined value; and comprising:
a first OR-gate, comprising:
a first input terminal configured to receive a polarity switch signal so as to be informed whether the polarity of the data line changes;
a second input terminal; and
an output terminal coupled to the control terminal of the first switch; and

a first AND-gate, comprising:
a first input terminal coupled to the data detection unit;
a second input terminal coupled to the polarity comparator; and
an output terminal coupled to the second input terminal of the first OR-gate;

a second logic unit, coupled to the control terminal of the second switch; configured to control if the second switch is turned on according to whether the polarity of the data line changes, the polarity of the data line, and whether the difference between the first sample data signal and the second sample data signal is larger than the predetermined value; and comprising:
a second OR-gate, comprising:
a first input terminal configured to receive the polarity switch signal so as to be informed whether the polarity of the data line changes;
a second input terminal; and
an output terminal coupled to the control terminal of the second switch;

a second AND-gate, comprising:
a first input terminal coupled to the data detection unit;
a second input terminal; and
an output terminal coupled to the second input terminal of the second OR-gate; and

an inverter, comprising:
an input terminal coupled to the polarity comparator; and
an output terminal coupled to the second input terminal of the second AND-gate; and

a polarity comparator, configured to compare the data signal with a voltage value with a predetermined voltage level so as to determine the polarity of the data line and the pixel coupled to the data line, comprising:
a first terminal coupled to the data line;
a second terminal coupled to the predetermined voltage level; and
an output terminal coupled to the first logic unit and the second logic unit;

wherein when the most-significant-bit of the first sample data signal is not identical to the most-significant-bit of the second sample data signal, the data line is selectively coupled to the first charge share line or the second charge share line according to a polarity of a common voltage signal of a pixel connected to the data line.

2. The electric charge share device of claim 1 , further comprising:
a capacitor comprising:
a first terminal electrically connected to the first charge share line, and
a second terminal connected to a ground.

3. The electric charge share device of claim 1 , further comprising:
a capacitor comprising:
a first terminal electrically connected to the second charge share line, and
a second terminal connected to a ground.

4. The electric charge share device of claim 1 , further comprising:
a capacitor comprising:
a first terminal electrically connected to the first charge share line, and
a second terminal connected to the second charge share line.

5. A data driver, electrically connected to a data line, comprising:
a first latch configured to output a first sample data signal;
a second latch electrically connected to the first latch and configured to output a second sample data signal;
a digital-to-analog convertor electrically connected to the second latch and configured to output a data signal to a pixel coupled to the data line;
a data detection unit coupled to the first latch and the second latch and configured to receive the first sample data signal and the second sample data signal;
a first charge share line;
a second charge share line; and
a data signal charge share unit coupled to the data line, the data detection unit, the first charge share line and the second charge share line, and comprising:
a first switch comprising:
a first terminal coupled to the first charge share line;
a second terminal coupled to the data line; and
a control terminal;

a second switch comprising:
a first terminal coupled to the second charge share line;
a second terminal coupled to the data line; and
a control terminal;

a first logic unit, coupled to the control terminal of the first switch; configured to control if the first switch is turned on according to whether a polarity of the data line changes, the polarity of the data line, and whether a difference between the first sample data signal and the second sample data signal is larger than a predetermined value; and comprising:
a first OR-gate, comprising:
a first input terminal configured to receive a polarity switch signal so as to be informed whether the polarity of the data line changes;
a second input terminal; and
an output terminal coupled to the control terminal of the first switch; and

a first AND-gate, comprising:
a first input terminal coupled to the data detection unit;
a second input terminal coupled to the polarity comparator; and
an output terminal coupled to the second input terminal of the first OR-gate;

a second logic unit, coupled to the control terminal of the second switch; configured to control if the second switch is turned on according to whether the polarity of the data line changes, the polarity of the data line, and whether the difference between the first sample data signal and the second sample data signal is larger than the predetermined value; and comprising:
a second OR-gate, comprising:
a first input terminal configured to receive the polarity switch signal so as to be informed whether the polarity of the data line changes;
a second input terminal; and
an output terminal coupled to the control terminal of the second switch;

a second AND-gate, comprising:
a first input terminal coupled to the data detection unit;
a second input terminal; and
an output terminal coupled to the second input terminal of the second OR-gate; and

an inverter, comprising:
an input terminal coupled to the polarity comparator; and
an output terminal coupled to the second input terminal of the second AND-gate; and

a polarity comparator, configured to compare the data signal with a voltage value with a predetermined voltage level so as to determine the polarity of the data line and the pixel coupled to the data line, comprising:
a first terminal coupled to the data line;
a second terminal coupled to the predetermined voltage level; and
an output terminal coupled to the first logic unit and the second logic unit;

wherein when the most-significant-bit of the first sample data signal is not identical to the most-significant-bit of the s

Assignees

• Au Optronics Corp

Inventors

• Chen Wei-Jyun
• Chung Chun-Fan
• Yeh Szu-Che

Classifications

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G3/3614 Primary

  Control of polarity reversal in general · CPC title

• G09G2310/0248

  Precharge or discharge of column electrodes before or after applying exact column voltages · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title