Wrapped source/drain contacts with enhanced area

US10084094B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10084094-B1
Application numberUS-201715462420-A
CountryUS
Kind codeB1
Filing dateMar 17, 2017
Priority dateMar 17, 2017
Publication dateSep 25, 2018
Grant dateSep 25, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor device and methods of forming the same include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer. The semiconductor fin is recessed below a height of the first and second dielectric layers. Source and drain extensions are grown from the recessed semiconductor fin. The first dielectric layer is recessed to expose an underside of and sidewalls of the source/drain extensions. Conductive contacts are formed around exposed portions of the source/drain extensions.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a plurality of semiconductor fins; fin extension formed on respective source and drain regions of the plurality of semiconductor fins that extend vertically and laterally beyond boundaries of the plurality of semiconductor fins; a first dielectric layer formed on sidewalls of the plurality of semiconductor fins and between the plurality of semiconductor fins, leaving at least a portion of sidewalls and an underside of the fin extension uncovered; conductive contacts formed in contact with a top surface, the underside, and sidewalls of the respective fin extensions; and a conductive liner directly between the fin extensions and the conductive contacts that covers a top surface of the first dielectric layer between the plurality of semiconductor fins. 2. The semiconductor device of claim 1 , wherein the first dielectric layer rises to a height above top surfaces of the plurality of semiconductor fins. 3. The semiconductor device of claim 1 , wherein the fin extensions of each semiconductor fin do not contact one another. 4. The semiconductor device of claim 1 , further comprising a second dielectric layer that bounds sidewalls of the conductive contacts. 5. The semiconductor device of claim 4 , wherein the first dielectric layer is formed from silicon nitride and wherein the second dielectric layer is formed from silicon dioxide.

Assignees

Inventors

Classifications

  • characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

  • Chemical etching · CPC title

  • by chemical means · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

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What does patent US10084094B1 cover?
Semiconductor device and methods of forming the same include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer. The semiconductor fin is recessed below a height of the first and second dielectric layers. Source and drain extensions are grown from the recessed semiconductor fin. The first dielectric layer is recessed …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L29/7851. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 25 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).