Methods of forming graphene contacts on source/drain regions of FinFET devices
US-9972537-B2 · May 15, 2018 · US
US10084094B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-10084094-B1 |
| Application number | US-201715462420-A |
| Country | US |
| Kind code | B1 |
| Filing date | Mar 17, 2017 |
| Priority date | Mar 17, 2017 |
| Publication date | Sep 25, 2018 |
| Grant date | Sep 25, 2018 |
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Semiconductor device and methods of forming the same include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer. The semiconductor fin is recessed below a height of the first and second dielectric layers. Source and drain extensions are grown from the recessed semiconductor fin. The first dielectric layer is recessed to expose an underside of and sidewalls of the source/drain extensions. Conductive contacts are formed around exposed portions of the source/drain extensions.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a plurality of semiconductor fins; fin extension formed on respective source and drain regions of the plurality of semiconductor fins that extend vertically and laterally beyond boundaries of the plurality of semiconductor fins; a first dielectric layer formed on sidewalls of the plurality of semiconductor fins and between the plurality of semiconductor fins, leaving at least a portion of sidewalls and an underside of the fin extension uncovered; conductive contacts formed in contact with a top surface, the underside, and sidewalls of the respective fin extensions; and a conductive liner directly between the fin extensions and the conductive contacts that covers a top surface of the first dielectric layer between the plurality of semiconductor fins. 2. The semiconductor device of claim 1 , wherein the first dielectric layer rises to a height above top surfaces of the plurality of semiconductor fins. 3. The semiconductor device of claim 1 , wherein the fin extensions of each semiconductor fin do not contact one another. 4. The semiconductor device of claim 1 , further comprising a second dielectric layer that bounds sidewalls of the conductive contacts. 5. The semiconductor device of claim 4 , wherein the first dielectric layer is formed from silicon nitride and wherein the second dielectric layer is formed from silicon dioxide.
characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title
Chemical etching · CPC title
by chemical means · CPC title
the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title
the material being a silicon oxide, e.g. SiO2 · CPC title
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