Virtual linebuffers for image signal processors

Patent metadata

Field	Value
Publication number	US-9749548-B2
Application number	US-201514603354-A
Country	US
Kind code	B2
Filing date	Jan 22, 2015
Priority date	Jan 22, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

First claim

What is claimed is:

1. An apparatus comprising:
image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S; and
a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL, the linebuffer including:
a full-size buffer having a width of W and a height of (S−1); and
a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

2. The apparatus of claim 1 , wherein the IPL is configured to produce the vertical slices of the output pixel data in a raster order.

3. The apparatus of claim 1 , wherein the IPL is a first IPL, the linebuffer is a first linebuffer, the image processing operation is a first image processing operation and the output pixel data is first output pixel data, the apparatus further comprising:
second IPL configured to perform a second image processing operation on the first output pixel data to produce second output pixel data in vertical slices of L pixels using L overlapping stencils of T×T pixels, L being greater than 1 and less than H, T being greater than or equal to 2; and
a second linebuffer operationally coupled between the first IPL and the second IPL, the second linebuffer configured to buffer the first output pixel data for the second IPL.

4. The apparatus of claim 3 , wherein the full-size buffer is a first full-size buffer and the sliding buffer is a first sliding buffer, the second linebuffer including:
a second full-size buffer having a width of W and a height of (T−1); and
a second sliding buffer having a width of TB and a height of L, TB being greater than or equal to T and less than W.

5. The apparatus of claim 3 , wherein L is equal to K and T is equal to S.

6. The apparatus of claim 3 , wherein L is not equal to K and T is not equal to S.

7. The apparatus of claim 1 , wherein an image processing function of the IPL is programmable.

8. The apparatus of claim 1 , wherein an image processing function of the IPL is fixed.

9. The apparatus of claim 1 , further comprising an image data source operationally coupled with the linebuffer, the image data source being configured to buffer the pixel data corresponding with the image.

10. The apparatus of claim 1 , wherein W is at least an order of magnitude greater than S.

11. The apparatus of claim 1 , wherein the full-size buffer includes a circular data buffer.

12. The apparatus of claim 1 , wherein the sliding buffer includes a first-in-first-out (FIFO) data buffer.

13. An apparatus comprising:
image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in slices having a height of K pixels and a width of J pixels using K×J overlapping stencils of S×S pixels, K and J being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S; and
a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL, the linebuffer including:
a full-size buffer having a width of W and a height of (S−1); and
a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S+(J−1) and less than W.

14. The apparatus of claim 13 , wherein the IPL is a first IPL, the linebuffer is a first linebuffer, the image processing operation is a first image processing operation and the output pixel data is first output pixel data, the apparatus further comprising:
second IPL configured to perform a second image processing operation on the first output pixel data to produce second output pixel data slices; and
a second linebuffer operationally coupled between the first IPL and the second IPL, the second linebuffer configured to buffer the first output pixel data for the second IPL.

15. The apparatus of claim 14 , wherein a slice of the second output pixel data slices produced by the second IPL has a height of K and a width of J.

16. The apparatus of claim 14 , wherein a slice of the second output pixel data slices produced by the second IPL has a height that is not equal to K and a width that is not equal J.

17. The apparatus of claim 13 , wherein the IPL is configured to produce the slices of the output pixel data in a raster order.

18. An image signal processor (ISP) comprising:
an image data source configured to buffer pixel data corresponding with an image having a width of W pixels and a height of H pixels;
a first image processing stage including:
first image processing logic (IPL) configured to perform a first image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce first output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S; and
a first linebuffer operationally coupled with the first IPL, the first linebuffer configured to buffer the pixel data for the first IPL, the first linebuffer including:
a first full-size buffer having a width of W and a height of (S−1); and
a first sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W; and

a second image processing stage including:
second IPL configured to perform a second image processing operation on the first output pixel data to produce second output pixel data in vertical slices of L pixels using L overlapping stencils of T×T pixels, L being greater than 1 and less than H, T being greater than or equal to 2; and
a second linebuffer operationally coupled between the first IPL and the second IPL, the second linebuffer configured to buffer the first output pixel data for the second IPL.

19. The ISP of claim 18 , wherein the second linebuffer includes:
a second full-size buffer having a width of W and a height of (T−1); and
a second sliding buffer having a width of TB and a height of L, TB being greater than or equal to T and less than W.

20. The ISP of claim 18 , wherein T is equal to S, and L is equal to K.

Assignees

• Google Inc

Inventors

• Zhu Qiuling
• Shacham Ofer
• Redgrave Jason Rupert
• Finchelstein Daniel Frederic
• Meixner Albert

Classifications

• G06T1/60 Primary

  Memory management · CPC title

• H04N5/262 Primary

  Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects {; Cameras specially adapted for the electronic generation of special effects} · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title