Line buffer unit for image processor

Patent metadata

Field	Value
Publication number	US-9756268-B2
Application number	US-201514694712-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	Apr 23, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

First claim

The invention claimed is:

1. An apparatus, comprising:
a line buffer unit circuit comprised of a plurality of line buffer interface unit circuits, each line buffer interface unit circuit to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory, the line buffer unit circuit having programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory, wherein said line buffer unit circuit includes control logic circuitry to:
assign at least one of the line buffer interface unit circuits to a free pool, that includes free ones of the line buffer interface unit circuits, after said at least one of the line buffer interface unit circuits has serviced its last consumer; and,
assign said at least one of the line buffer interface unit circuits from the free pool to another line group.

2. The apparatus of claim 1 wherein the line buffer unit circuit includes circuitry to comprehend an expression of at least one X, Y location within an image frame.

3. The apparatus of claim 1 wherein said at least one of the line buffer interface unit circuits includes circuitry to comprehend an expression of at least one X, Y location within an image frame and convert the expression into a linear memory address.

4. The apparatus of claim 1 wherein said at least one of the line buffer interface unit circuits supports a full line group mode.

5. The apparatus of claim 1 wherein said at least one of the line buffer interface unit circuits supports a virtually tall line group mode.

6. The apparatus of claim 1 wherein said at least one of the line buffer interface unit circuits is coupled to receive any of the following information from a configuration register space:
a) number of channels in image information;
b) number of consumers of a line group;
c) full line group unit width;
d) full line group height;
e) a dimension of a smaller portion of a line group.

7. The apparatus of claim 1 wherein the line buffer unit circuit includes register space to store a base address for a line group.

8. The apparatus of claim 1 wherein the line buffer unit circuit includes circuitry to determine a base address for a line group based on X,Y coordinate information derived from a software development environment.

9. The apparatus of claim 1 wherein the line buffer unit circuit includes pointer circuitry to comprehend where next image data to be fetched is located in the memory.

10. A non-transitory machine readable storage medium containing program code for compilation and loading of a formatted description of an electronic circuit for fabrication into a semiconductor chip thereby causing the semiconductor chip to operate as the electronic circuit, the electronic circuit comprising:
a line buffer unit comprised of a plurality of a line buffer interface units, each line buffer interface unit to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory, the line buffer unit having programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory, wherein said line buffer unit includes control logic circuitry to:
assign at least one of the line buffer interface units to a free pool, that includes free ones of the line buffer interface units, after said at least one of the line buffer interface units has serviced its last consumer; and,
assign said at least one of the line buffer interface units from the free pool to another line group.

11. The non-transitory machine readable storage medium of claim 10 wherein the line buffer unit includes circuitry to comprehend an expression of at least one X, Y location within an image frame.

12. The non-transitory machine readable storage medium of claim 10 wherein said at least one of the line buffer interface units includes circuitry to comprehend an expression of at least one X, Y location within an image frame and convert the expression into a linear memory address.

13. The non-transitory machine readable storage medium of claim 10 wherein said at least one of the line buffer interface units supports a full line group mode.

14. The non-transitory machine readable storage medium of claim 10 wherein said at least one of the line buffer interface units supports a virtually tall line group mode.

15. The non-transitory machine readable storage medium of claim 10 wherein said at least one of the line buffer interface units is coupled to receive any of the following information from a configuration register space:
a) number of channels in image information;
b) number of consumers of a line group;
c) full line group unit width;
d) full line group height;
e) a dimension of a smaller portion of a line group.

16. The non-transitory machine readable storage medium of claim 10 wherein the line buffer unit includes register space to store a base address for a line group.

17. The non-transitory machine readable storage medium of claim 10 wherein the line buffer unit includes circuitry to determine a base address for a line group based on X,Y coordinate information derived from a software development environment.

18. The non-transitory machine readable storage medium of claim 10 wherein the line buffer unit includes pointer circuitry to comprehend where next image data to be fetched is located in the memory.

19. A computing system, comprising:
a plurality of processing cores;
an image processor, said image processor comprising a line buffer unit comprised of a plurality of a line buffer interface units, each line buffer interface unit to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory, the line buffer unit having programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory, wherein said line buffer unit includes control logic circuitry to:
assign at least one of the line buffer interface units to a free pool, that includes free ones of the line buffer interface units, after said at least one of the line buffer interface units has serviced its last consumer; and,
assign said at least one of the line buffer interface units from the free pool to another line group.

20. The computing system of claim 19 wherein the line buffer unit includes circuitry to comprehend an expression of at least one X, Y location within an image frame.

21. The computing system of claim 19 wherein said at least one of the line buffer interface units includes circuitry to comprehend an expression of at least one X, Y location within an image frame and convert the expression into a linear memory address.

22. The computing system of claim 19 wherein said at least one of the line buffer interface units supports a full line group mode.

23. The computing system of claim 19 wherein said at least one of the line buffer interface units is coupled to receive any of the following information from a configuration register space:
a) number of c

Assignees

• Google Inc

Inventors

• Desai Neeti
• Meixner Albert
• Zhu Qiuling
• Redgrave Jason Rupert
• Shacham Ofer
• Finchelstein Daniel Frederic

Classifications

• H04N25/701 Primary

  Line sensors · CPC title

• H04N5/91

  Television signal processing therefor · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• H04N5/3692 Primary

  Electricity · mapped topic