Sub-pixel unit, display panel, and display apparatus and drive method therefor

US11183102B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11183102-B2
Application numberUS-201916962614-A
CountryUS
Kind codeB2
Filing dateDec 24, 2019
Priority dateJan 4, 2019
Publication dateNov 23, 2021
Grant dateNov 23, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a sub-pixel unit, a display panel, a display apparatus, and a driving method of the display apparatus, which belongs to the field of display technology. The sub-pixel unit includes a plurality of sub-pixels; any of the sub-pixels includes a display module, a control module, and a driving module; wherein the control module is connected to a second gate line, a data line, a first voltage end and a first node, and configured to receive a data signal on the data line under control of a signal on the second gate line, and control one of the data line and the first voltage end to be connected to the first node according to the received data signal; and the driving module is connected to a first gate line, the first node and the display module, and configured to drive the display module according to a signal on the first node under control of a signal on the first gate line.

First claim

Opening claim text (preview).

What is claimed is: 1. A sub-pixel unit, comprising a plurality of sub-pixels, wherein any one of the sub-pixels comprises: a display sub-circuit; a control sub-circuit connected to a second gate line, a data line, a first voltage end, and a first node, and configured to receive a data signal on the data line under control of a signal on the second gate line, and control one of the data line and the first voltage end to be connected to the first node according to the received data signal; and a driving sub-circuit connected to a first gate line, the first node, and the display sub-circuit, and configured to drive the display sub-circuit according to a signal on the first node under control of a signal on the first gate line, wherein the driving sub-circuit is configured to drive the display sub-circuit to be in one of a bright state and a dark state; and the display sub-circuits of at least two sub-pixels have different display brightness in the bright state. 2. The sub-pixel unit according to claim 1 , wherein the second gate line is one of a plurality of second gate lines, and control sub-circuits of different sub-pixels are connected to different ones of the plurality of second gate lines. 3. The sub-pixel unit according to claim 1 , wherein the first gate line is one of a plurality of first gate lines, and driving sub-circuits of adjacent sub-pixels are connected to the same one of the first gate lines. 4. The sub-pixel unit according to claim 1 , wherein the display sub-circuits of at least two sub-pixels have different display areas. 5. The sub-pixel unit according to claim 1 , wherein the sub-pixel unit comprises: a first sub-pixel, wherein the display sub-circuit of the first sub-pixel comprises a first display sub-circuit and a second display sub-circuit; and a second sub-pixel, wherein the display sub-circuit of the second sub-pixel comprises a third display sub-circuit, wherein the first display sub-circuit and the second display sub-circuit are provided on two sides of the third display sub-circuit. 6. The sub-pixel unit according to claim 1 , wherein the control sub-circuit comprises: a switching sub-circuit connected to the data line and the second gate line, and configured to output the data signal on the data line to a second node under control of the signal on the second gate line; a latch sub-circuit connected to the second node, a second voltage end, a third voltage end, a third node, and a fourth node, and configured to output one of a signal on the second voltage end and a signal on the third voltage end to the third node, and output another one of the signal on the second voltage end and the signal on the third voltage end to the fourth node, under control of the second node, the second voltage end, and the third voltage end; a selection sub-circuit connected to the first node, the third node, the fourth node, the data line, and the first voltage end, and configured to control one of the data line and the first voltage end to be connected to the first node, under control of a signal on the third node and a signal on the fourth node. 7. The sub-pixel unit according to claim 6 , wherein the selection sub-circuit comprises: a first selection switch having an input end connected to the data line, an output end connected to the first node, and a control end connected to the third node; and a second selection switch having an input end connected to the first voltage end, an output end connected to the first node, and a control end connected to the fourth node, wherein the first selection switch and the second selection switch are selectively turned on under control of the third node and the fourth node. 8. The sub-pixel unit according to claim 6 , wherein the switching sub-circuit comprises a first thin film transistor, and the first thin film transistor has an input end connected to the data line, an output end connected to the latch sub-circuit, and a control end connected to the second gate line. 9. The sub-pixel unit according to claim 6 , wherein: the latch sub-circuit comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor; the second thin film transistor has one end connected to the second voltage end and the other end connected to a fifth node; the third thin film transistor has one end connected to the fifth node and the other end connected to the third voltage end; control ends of both the second thin film transistor and the third thin film transistor are connected to the second node, the third node, and a sixth node; the fourth thin film transistor has one end connected to the second voltage end and the other end connected to the sixth node; the fifth thin film transistor has one end connected to the sixth node and the other end connected to the third voltage end; and control ends of both the fourth thin film transistor and the fifth thin film transistor are connected to the fourth node and the fifth node. 10. The sub-pixel unit according to claim 1 , wherein the driving sub-circuit comprises a driving switch having an input end connected to the first node, a control end connected to the first gate line, and an output end connected to the display sub-circuit. 11. The sub-pixel unit according to claim 1 , wherein: the control sub-circuit comprises a switching sub-circuit, a latch sub-circuit, and a selection sub-circuit; the switching sub-circuit comprises a first thin film transistor, and the first thin film transistor has an input end connected to the data line, an output end connected to the latch sub-circuit, and a control end connected to the second gate line; the latch sub-circuit comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor; the second thin film transistor has one end connected to the second voltage end and the other end connected to a fifth node; the third thin film transistor has one end connected to the fifth node and the other end connected to the third voltage end, control ends of both the second thin film transistor and the third thin film transistor are connected to the second node, the third node and a sixth node, the fourth thin film transistor has one end connected to the second voltage end and the other end connected to the sixth node; the fifth thin film transistor has one end connected to the sixth node and the other end connected to the third voltage end, control ends of both the fourth thin film transistor and the fifth thin film transistor are connected to the fourth node and the fifth node; the selection sub-circuit comprises a sixth thin film transistor and a seventh thin film transistor, wherein the sixth thin film transistor has an input end connected to the data line, an output end connected to the first node, and a control end connected to the third node, the seventh thin film transistor has an input end connected to the first voltage end, an output end connected to the first node, and a control end connected to the fourth node; and the driving sub-circuit comprises an eighth thin film transistor, the eighth thin film transistor having an input end connected to the first node, a control end connected to the first gate line, and an output end connected to the display sub-circuit. 12. A display panel, comprising: a first gate line, a second gate line, a data line, a first voltage end, and a sub-pixel unit, wherein the sub-pixel unit comprises a plurality of sub-pixels, and any one of the sub-pixels comprises: a display sub-circuit; a control sub-circuit connected to the second gate line, the data line, the first voltage end, and a

Assignees

Inventors

Classifications

  • Display of colours (specific for liquid crystal displays G09G3/3607) · CPC title

  • G09G3/2074Primary

    using sub-pixels · CPC title

  • with pixel circuitry controlling the voltage across the light-emitting element · CPC title

  • Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements · CPC title

  • using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

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What does patent US11183102B2 cover?
The present disclosure provides a sub-pixel unit, a display panel, a display apparatus, and a driving method of the display apparatus, which belongs to the field of display technology. The sub-pixel unit includes a plurality of sub-pixels; any of the sub-pixels includes a display module, a control module, and a driving module; wherein the control module is connected to a second gate line, a dat…
Who is the assignee on this patent?
Beijing Boe Optoelectronics Tech Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/2074. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 23 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).