Liquid crystal display device

Patent metadata

Field	Value
Publication number	US-10459569-B2
Application number	US-201816040915-A
Country	US
Kind code	B2
Filing date	Jul 20, 2018
Priority date	Oct 23, 2015
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

A liquid crystal display device includes: a display unit configured to pixels in a display region, a pixel drive circuit configured to apply voltage to liquid crystals, a memory configured to store therein a setting signal indicating whether to apply voltage to the liquid crystals in the display region, and two switch elements for switching coupling with the pixel drive circuit; and a controller configured to rewrite the setting signal stored in the memory when a mode in which the display unit is operated is switched, between a first mode causing the display unit to perform display output in accordance with a gradation signal generated based on image data, and a second mode causing the display unit to perform display output in accordance with the setting signal stored in the memory.

First claim

What is claimed is:

1. A display device comprising:
a pixel electrode;
a switch circuit that includes a plurality of switches and that is coupled to the pixel electrode;
a memory that is configured to store a setting signal and that is coupled to the switch circuit;
a signal line coupled to the switch circuit;
a controller configured to set a display operation mode to one of a first mode and a second mode; and
a wire coupled to the switch circuit,
wherein:
in the first mode, the signal line is supplied with a gradation signal that is generated based on image data, and the switch circuit transmits the gradation signal through the signal line to the pixel electrode; and
in the second mode:
the signal line is supplied with a first signal, and the switch circuit transmits the first signal to the pixel electrode based on the setting signal stored in the memory;
the memory outputs a first memory signal or a second memory signal to the switch circuit based on the setting signal;
the switch circuit transmits
when the switch circuit receives the first memory signal, the first signal from the signal line to the pixel electrode, and
when the switch circuit receives the second memory signal, a second signal from the wire to the pixel electrode; and

the second signal is different from the first signal.

2. The display device according to claim 1 , the second signal is inverted oppositely in phase of the first signal.

3. The display device according to claim 1 , further comprising:
a second electrode opposed to the first electrode,
wherein,
in the second mode:
the second electrode is supplied with a third signal; and
the third signal is either equal to the first signal and different from the second signal, or equal to the second signal and different from the first signal.

4. The display device according to claim 1 ,
wherein the switch circuit includes a first switch and a second switch, wherein the first switch is configured to receive the first memory signal and is arranged between the signal line and the pixel electrode, and
wherein the second switch is configured to receive the second memory signal and is arranged between the wire and the pixel electrode.

5. The display device according to claim 1 ,
wherein, in the first mode:
the memory outputs the first memory signal to the switch circuit based on the setting signal; and
the switch circuit transmits the gradation signal through the signal line to the pixel electrode based on the first memory signal.

6. The display device according to claim 1 ,
wherein, in the first mode:
the memory outputs the first memory signal to the switch circuit based on the setting signal; and
the switch circuit transmits the gradation signal through the signal line to the pixel electrode in accordance with the first memory signal.

7. The display device according to claim 1 , further comprising:
a switch arranged between the signal line and the memory, and
wherein the signal line is supplied with the setting signal, and
wherein the switch transmits the setting signal with the signal line to the memory.

8. The display device according to claim 1 ,
wherein the controller is configured to control signal input to the pixel electrode in frame periods,
wherein one of the frame periods includes:
a first duration in which the memory receives the setting signal for setting the switch circuit to couple the signal line to the pixel electrode;
a second duration in which the gradation signal is output to the pixel electrode in the first mode; and
a third duration in which the setting signal is output to the memory in the second mode.

9. The display device according to claim 8 ,
wherein the first duration and the second duration are continuous in at least one of the frame periods.

10. The display device according to claim 8 ,
wherein the second duration and the third duration that are continuous in at least one of the frame periods.

11. The display device according to claim 1 , wherein the wire is different from the signal line,
wherein the setting signal includes a first setting signal and a second setting signal, and
wherein the switch circuit couples
when the memory receives a first setting signal, the signal line and the pixel electrode, and
when the memory receives a second setting signal, the wire and the pixel electrode.

12. The display device according to claim 11 ,
wherein the controller is configured to control signal input to the pixel electrode in frame periods, and
wherein one of the frame periods includes at least one of:
a first duration in which the memory receives the first setting signal;
a second duration in which the gradation signal is output to the pixel electrode in the first mode; and
a third duration in which the first setting signal or the second setting signal is output to the memory in the second mode.

13. The display device according to claim 12 , further comprising:
a plurality of pixels, each of which includes the pixel electrode, the switch circuit, and the memory,
wherein the controller is configured to control signal input to the plurality of pixel in the frame periods,
wherein, in the first duration, the memory receives the first setting signal in all of the pixels, and
wherein, in the third duration, the memory receives the first setting signal or the second setting signal.

14. The display device according to claim 13 ,
wherein the plurality of pixels includes a first pixel and a second pixel, and
wherein, in the first duration, the memory of the first pixel and the memory of the second pixel simultaneously receive the first setting signal.

15. The display device according to claim 13 ,
wherein the plurality of pixels includes a first pixel and a second pixel, and
wherein, in the third duration, the memory of the first pixel receives the first setting signal, and the memory of the second pixel receives the second setting signal.

16. The display device according to claim 13 ,
wherein the plurality of pixels includes a first pixel and a second pixel, and
wherein, in the third duration, the memory of the first pixel receives the first setting signal at a first timing, and the memory of the first pixel receives the second setting signal at a second timing different from the first timing.

17. The display device according to claim 1 , further comprising:
a first scanning line configured to transmit a first scanning signal indicating whether to couple the pixel electrode and the signal line; and
a second scanning line configured to transmit a second scanning signal indicating whether to couple the memory and the signal line.

18. The liquid crystal display device according to claim 17 , further comprising:
a touch detecting circuit configured to detect a touch operation in a touch detection duration,
wherein no signal transmission is performed through the first scanning line and the second scanning line in the touch detection duration.

19. The display device according to claim 1 , further comprising:
a second electrode opposed to the first electrode,
wherein, in the first mode, the second electrode is supplied with a third signal,
wherein, in the second mode, the second electrode is supplied with a fourth signal, and
wherein a frequency of the third signal is different from a frequency of the fourth signal.

Assignees

• Japan Display Inc

Inventors

• Takano Daijiro

Classifications

• G02F2201/123

  pixel · CPC title

• G02F2201/52

  RGB geometrical arrangements · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G09G2310/0235

  Field-sequential colour display · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title