Display device, method of driving display device, and electronic appliance

Patent metadata

Field	Value
Publication number	US-9495897-B2
Application number	US-201514716254-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	Mar 1, 2012
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A display device in which pixels having a memory function are arranged includes a driving unit that performs display driving in a driving method that obtains a middle gradation by temporally changing gradation of each of the pixels in one period in which a plurality of frames are assumed, wherein the driving unit is configured to discontinuously write lower bits and higher bits of gradation data with respect to the pixels in a scanning direction in a unit of one line or a plurality of lines.

First claim

The invention is claimed as follows:

1. A display device in which pixels having a memory function are arranged, the display device comprising:
a driving unit configured to perform display driving in a driving method that obtains a middle gradation by temporally changing gradation of each of the pixels in one period in which a plurality of frames are assumed,
wherein the driving unit is configured to discontinuously write:
in a scanning unit including at least one scanning line, lower bits or higher bits of gradation data with respect to the pixels in a scanning direction; and
in one frame, only one side of data of lower bits and higher bits of the gradation data with respect to the pixels in the scanning direction, and
wherein the discontinuities exist between the scanning units.

2. The display device according to claim 1 , wherein the one period, the driving unit is configured to insert writing of other data of the lower bits and the higher bits before finishing writing of entire lines with respect to one side of data of the lower bits and the higher bits.

3. The display device according to claim 2 , wherein the driving unit is configured to perform, in the one period, writing of the data of the lower bits and the higher bits by interlaced scanning in a unit of one line or a plurality of lines, is configured to perform writing of other data of the lower bits and the higher bits by interlaced scanning with respect to the same lines as the one side of data, and is configured to then sequentially perform writing of the one side of data and other data by interlaced scanning with respect to the lines interlaced by an initial writing.

4. The display device according to claim 1 , wherein the driving unit is configured to perform discontinuous writing of one side of data of the lower bits and the higher bits in a certain frame in the scanning direction, and is configured to perform discontinuous writing of other data of the lower bits and the higher bits in a next frame in the scanning direction.

5. The display device according to claim 4 , wherein the driving unit is configured to first perform writing of the respective data of the lower bits and the higher bits in one frame by interlaced scanning with respect to an odd-numbered line or an odd numbered-line group, and is configured to then perform writing by interlaced scanning with respect to an even-numbered line or an even-numbered line group.

6. The display device according to claim 1 , wherein the pixel includes a plurality of sub-pixels, and the gradation is displayed by a combination of areas of the plurality of sub-pixels.

7. The display device according to claim 6 , wherein a pixel electrode of the pixel is divided into a plurality of electrodes for the plurality of sub-pixels, and the gradation display is performed by a combination of areas of the plurality of electrodes.

8. The display device according to claim 7 , wherein the plurality of electrodes includes three electrodes, and the gradation display is performed by a combination of areas of the middle electrode and the two electrodes across the middle electrode.

9. The display device according to claim 8 , wherein the two electrodes have the same area.

10. The display device according to claim 8 , wherein the two electrodes are electrically connected to each other and are driven by one driving circuit.

11. A method of driving a display device in which pixels having a memory function are arranged and which performs display driving in a driving method that obtains a middle gradation by temporally changing gradation of each of the pixels in one period in which a plurality of frames are assumed, the method comprising:
discontinuously writing, in a scanning unit including at least one scanning line, lower bits or higher bits of gradation data with respect to the pixels in a scanning direction; and
discontinuously writing, in one frame, only one side of data of lower bits and higher bits of the gradation data with respect to the pixels in the scanning direction,
wherein the discontinuities exist between the scanning units.

12. An electronic appliance comprising:
a display device in which pixels having a memory function are arranged and which includes a driving unit that performs display driving in a driving method that obtains a middle gradation by temporally changing gradation of each of the pixels in one period in which a plurality of frames are assumed,
wherein the display device is configured to discontinuously write:
in a scanning unit including at least one scanning line, lower bits or higher bits of gradation data with respect to the pixels in a scanning direction; and
in one frame, only one side of data of lower bits and higher bits of the gradation data with respect to the pixels in the scanning direction, and
wherein the discontinuities exist between the scanning units.

Assignees

• Japan Display Inc

Inventors

• Teranishi Yasuyuki
• Nakanishi Takayuki
• Tanaka Toshihiko
• Kurasawa Hayato

Classifications

• G09G3/2022

  using sub-frames · CPC title

• G09G3/2077 Primary

  by a combination of two or more gradation control methods · CPC title

• G09G2300/0857

  Static memory circuit, e.g. flip-flop · CPC title

• G09G2310/04

  Partial updating of the display screen · CPC title

• G09G5/10

  Intensity circuits · CPC title