Semiconductor package having multi-level and multi-directional shape narrowing vias

Patent metadata

Field	Value
Publication number	US-11177205-B2
Application number	US-201916454304-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Dec 18, 2018
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.

First claim

What is claimed is:

1. A semiconductor package comprising:
a redistribution substrate having first and second surfaces disposed opposite to each other, and including an insulation member, a plurality of redistribution layers disposed on different levels in the insulation member, and a redistribution via connecting the redistribution layers disposed on neighboring levels and having a shape narrowing from the second surface toward the first surface in a first direction;
a plurality of under bump metallurgy (UBM) layers, each of the plurality of UBM layers including a UBM pad disposed on the first surface of the redistribution substrate, and a UBM via connected to a redistribution layer adjacent to the first surface among the plurality of redistribution layers and connected to the UBM pad, and having a shape narrowing in a second direction opposite to the first direction; and
at least one semiconductor chip disposed on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to a redistribution layer adjacent to the second surface among the plurality of redistribution layers,
wherein the UBM pad has a recessed portion in an area overlapping with the UBM via,
wherein each of the plurality of UBM layers has a thickness greater than a thickness of the redistribution layer adjacent to the first surface, and each of the plurality of UBM layers has a thickness of 10 μm or more, and
wherein the insulation member includes a plurality of first insulation layers, each of the plurality of first insulation layers surrounding the redistribution via, and a second insulating layer surrounding the UBM via, and the plurality of first insulation layers and the second insulating layer comprise a photosensitive insulating material.

2. The semiconductor package according to claim 1 ,
wherein the redistribution substrate further comprises a plurality of bonding pads disposed on the second surface, each of the plurality of bonding pads connected to a corresponding one of the plurality of contact pads, and
wherein each of the plurality of bonding pads has a via portion partially passing through the insulation member and connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.

3. The semiconductor package according to claim 2 , wherein the via portion has a shape narrowing in the first direction.

4. The semiconductor package according to claim 1 , wherein the insulation member has a plurality of holes for exposing a portion of the redistribution layer adjacent to the second surface, and the plurality of contact pads are respectively connected to the redistribution layer adjacent to the second surface through the plurality of holes.

5. The semiconductor package according to claim 1 , wherein the insulation member comprises a photosensitive insulating material.

6. The semiconductor package according to claim 1 , wherein the UBM pad has a portion extending along a surface of the insulation member located on the first surface of the redistribution substrate.

7. The semiconductor package according to claim 1 , further comprising:
a passivation layer disposed on the first surface of the redistribution substrate and exposing at least a portion of the plurality of UBM layers; and
a plurality of external connectors disposed on the plurality of UBM layers, respectively.

8. The semiconductor package according to claim 7 , wherein the passivation layer comprises a photosensitive insulating material.

9. The semiconductor package according to claim 7 , wherein the passivation layer comprises an insulating material different from a material comprising the insulation member.

10. The semiconductor package according to claim 1 , further comprising:
a molding portion disposed on the second surface of the redistribution substrate and covering the at least one semiconductor chip.

11. A semiconductor package comprising:
a redistribution substrate having first and second surfaces disposed to opposite each other, and including an insulation member, and a plurality of redistribution layers disposed on different levels in the insulation member;
an under bump metallurgy (UBM) layer including a UBM pad disposed on the first surface of the redistribution substrate, and a UBM via electrically connecting the UBM pad and the plurality of redistribution layers, and having a shape narrowing in a direction from the first surface toward the second surface; and
at least one semiconductor chip disposed on the second surface of the redistribution substrate, and having a contact pad electrically connected to the plurality of redistribution layers,
wherein the plurality of redistribution layers includes:
a first redistribution layer disposed on a level adjacent to the first surface in the insulation member and composed of a planar conductive pattern, and
a plurality of second redistribution layers disposed on different levels in the insulation member, each of the plurality of second redistribution layers having a redistribution via connected to the first redistribution layer or a neighboring second redistribution layer of the plurality of second redistribution layers and having a shape narrowing from the second surface toward the first surface,

wherein the UBM pad has a recessed portion in an area overlapping with the UBM via,
wherein each of the plurality of UBM layers has a thickness greater than a thickness of the redistribution layer adjacent to the first surface, and each of the plurality of UBM layers has a thickness of 10 μm or more, and
wherein the insulation member includes a plurality of first insulation layers, each of the plurality of first insulation layers surrounding the redistribution via, and a second insulating layer surrounding the UBM via, and the plurality of first insulation layers and the second insulating layer comprise a photosensitive insulating material.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jung Ho
• Kim Jong Youn
• Bae Min Jun

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title