Phase interpolator calibration

Patent metadata

Field	Value
Publication number	US-9698968-B2
Application number	US-201615058625-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Jan 14, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

First claim

What is claimed is:

1. A calibration apparatus for a phase interpolator (PI), the interpolator having:
a first phase addition mixer and a second phase addition mixer, the first phase addition mixer generating a first adjusted phase interpolated clock signal representing a first phase position of the phase interpolator according to a first bias current applied to said first phase addition mixer in response to a received first digital code value, and the second phase addition mixer generating a second adjusted phase interpolated clock signal representing a second phase position of the phase interpolator offset from said first phase position according to a second bias current applied to said second phase addition mixer in response to a received second digital code value, said apparatus comprising:
a phase detector for receiving said respective first adjusted phase interpolated clock signal, and a respective second adjusted phase interpolated clock signal and generating a difference signal according to a detected phase error difference;
a charge pump integrator circuit for receiving said difference signal and generating an output voltage ramp signal having a slope proportional to said detected phase error difference;
and a comparator device receiving said output ramp signal and comparing output voltage ramp signal against a predetermined threshold, said comparator generating an output signal responsive to said comparison, said output signal representing a direction for adjustment of either said first clock phase or said second offset clock phase, or both to correct a detected phase error; and
a logic circuit receiving said output signal and applying logic for one of: determining a first calibration code value for adjusting the first bias current applied to said first phase addition mixer, determining a second calibration code value for adjusting the second bias current applied to said second phase addition mixer to achieve a desired phase offset between said first and second clock signals that is within a predefined upper and lower threshold limit, or both determining a first calibration code value for adjusting the first bias current applied to said first phase addition mixer and determining a second calibration code value for adjusting the second bias current applied to said second phase addition mixer to achieve the desired phase offset,
each said determined first calibration code value and second calibration code value for correcting a non-linearity error of a phase position at an output of the phase interpolator with respect to a respective received first digital code value or received second digital code value.

2. The calibration apparatus as claimed in claim 1 , wherein said first phase addition mixer generates said first clock signal of a first phase according to said first bias current applied to said first mixer according to weights of a first digital to analog converter (first DAC) responsive to said received first digital code value, and the second phase addition mixer generates a second clock signal of a second phase offset from said first phase according to said second bias current applied to said second mixer according to weights of a second digital to analog converter (second DAC) responsive to said received second digital code value, said apparatus further comprising:
a first trim DAC responsive to said first calibration code value for trimming said weights of said first DAC, and,
a second trim DAC responsive to said second calibration code value for trimming said weights of said second DAC, wherein trimming either or both said first DAC and second DAC corrects said phase error difference.

3. The calibration apparatus as claimed in claim 2 , wherein said PI is configurable to provide a plurality of combinations of the first clock signal of a first phase and the second clock signal of the phase offset therefrom to achieve a desired phase adjustment therebetween, said apparatus configured to obtain, for each one of said plurality of combinations in successive calibration steps, the first calibration code value configured for adjusting the first bias current applied to said first phase addition mixer, and the second calibration code value configured for adjusting a second bias current applied to said second phase addition mixer, said apparatus further comprising:
a memory storage device for storing and accessing said first calibration code value and said second calibration code value for each said combination of said plurality,
wherein said PI apparatus subsequently uses said stored first calibration code value and said second calibration code value for correcting said non-linearity error of the phase position at the output of the phase interpolator with respect to the received digital code value.

4. The apparatus as claimed in claim 3 , wherein said PI is configurable to provide up to 64 combinations of first clock and second phase offset clock signals to provide up to 64 output clock phase adjustments based on corresponding combinations of received first and second digital code values.

5. The apparatus as claimed in claim 3 wherein a combination of a received first digital code value and second digital code value is set at a fixed offset relative to each other to generate a respective first clock signal and second offset clock signal at a particular calibration step, wherein said phase detector comprises an XOR phase detector for XORing said first clock and second offset clock signals to produce pulses having widths proportional to the phase difference between said first and second clocks, said produced pulses operating to activate a switch in said charge pump integrator circuit.

6. The apparatus as claimed in claim 5 wherein said charge pump integrator circuit produces a differential voltage output at a respective first and second output node thereof that is proportional to said detected phase error difference.

7. The apparatus as claimed in claim 6 wherein said comparator device is a voltage comparator of a differential configuration having a first upper threshold and a second lower threshold, a voltage between said first and second thresholds defining an acceptable phase difference, said differential comparator device:
receiving said differential voltage output and comparing said differential voltage output against both said first upper threshold and against said second pre-determined threshold in a single phase comparison cycle, and generating said output signal representing said phase adjustment direction of a phase of said first clock or second clock when said output differential voltage is above said first upper threshold or below said second lower threshold in said single phase comparison cycle.

8. The apparatus as claimed in claim 7 wherein said logic circuit performs at each successive calibration step, a trimming procedure to obtain said first calibration code and second calibration code values, said trimming procedure alternating said determining of said first calibration code value and the determining of said second calibration code values.

9. The apparatus as claimed in claim 8 wherein said logic circuit performs during said trimming procedure, alternately one of: incrementing or decrementing either the first calibration code value or the second calibration code value according to a fixed offset code value.

10. The apparatus as claimed in claim 4 , further comprising:
obtaining an optimum code_offset value between the first digital code value input to said first mixer and second digital code value input to said second mixer during calibration so as to satisfy a condition of: a ‘remainder(total_rotator_steps/code_offset)=1’ where a total_rotator_steps corresponds to a total number of combinati

Assignees

• IBM

Inventors

• Bonaccio Anthony R
• Buchholtz Timothy C
• Cheeranthodi Rajesh
• Rangan Giri N
• Rylov Sergey V

Classifications

• H04L7/0079

  Receiver details · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H04L7/0029 Primary

  interpolation of received data signal · CPC title

• H04L27/3405

  Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power · CPC title

• H04L7/0332

  with an integrator-detector · CPC title