Calibration of an interpolative divider using a virtual phase-locked loop

Patent metadata

Field	Value
Publication number	US-10833682-B1
Application number	US-201916582266-A
Country	US
Kind code	B1
Filing date	Sep 25, 2019
Priority date	Sep 25, 2019
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

First claim

What is claimed is:

1. A clock generator comprising:
an interpolative divider comprising a phase interpolator and a multi-modulus divider, the interpolative divider being configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal; and
a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code, wherein the calibration circuit comprises:
a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal; and
an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

2. The clock generator, as recited in claim 1 , further comprising:
an integer frequency divider configured to generate a frequency-divided output clock signal in response to the output clock signal and an integer code; and
a time-to-digital converter configured to generate the timestamp signal, the timestamp signal including digital codes corresponding to edges of a frequency-divided clock signal based on the clock signal.

3. The clock generator, as recited in claim 1 , wherein the phase-locked loop includes two integrators and is configured to cause the digital phase error signal to have zero mean.

4. The clock generator, as recited in claim 1 , wherein the phase-locked loop comprises an integrator programmed with a free-running period estimate to generate the reference timestamp signal with the same period as the timestamp signal.

5. The clock generator, as recited in claim 1 , wherein the reference timestamp signal is a spur-attenuated version of the timestamp signal.

6. The clock generator, as recited in claim 1 , wherein the phase-locked loop further comprises:
a wrap detection and correction circuit configured to compensate for rollover error caused by using less than all bits of the timestamp signal by the phase-locked loop and the adaptive loop.

7. The clock generator, as recited in claim 1 , further comprising:
a first frequency divider configured to generate an integer-divided output clock signal;
a second frequency divider configured to provide an integer-divided clock signal; and
a time-to-digital converter configured to generate the timestamp signal based on the integer-divided output clock signal and the integer-divided clock signal.

8. The clock generator, as recited in claim 1 , wherein the digital phase error signal is a difference between the reference timestamp signal and the timestamp signal.

9. The clock generator, as recited in claim 1 , wherein the adaptive loop includes a least mean squares filter.

10. The clock generator, as recited in claim 1 , wherein the phase-locked loop comprises:
a digital circuit configured to compute a difference between the timestamp signal and the reference timestamp signal to generate the digital phase error signal;
a first integrator configured to generate an integrated phase error signal based on the digital phase error signal;
a proportional circuit path configured to generate a proportional phase error signal based on the digital phase error signal;
a second digital circuit configured to compute a sum of the integrated phase error signal and the proportional phase error signal;
a second integrator responsive to the sum;
a free running period estimator circuit configured to generate an expected timestamp signal; and
a third digital circuit configured to generate the reference timestamp signal based on the sum of the expected timestamp signal and an output of the second integrator.

11. The clock generator, as recited in claim 1 , further comprising:
a select circuit configured to selectively output an active output clock signal generated by one of a plurality of output interpolative dividers;
a shared integer frequency divider configured to generate a frequency-divided active clock signal in response to the active output clock signal and a corresponding integer code; and
a shared time-to-digital converter configured to generate a corresponding timestamp signal based on edges of the frequency-divided active clock signal,
wherein the calibration circuit is further configured to generate an active phase interpolator calibration signal based on the clock signal, the active output clock signal, and a corresponding phase interpolator code, the active phase interpolator calibration signal being used to periodically update the phase interpolator calibration signal.

12. A method comprising:
generating an output clock signal using an interpolative divider responsive to a clock signal, a control code, and a phase interpolator calibration signal; and
generating the phase interpolator calibration signal based on the clock signal, the output clock signal, and a phase interpolator code, wherein
generating the phase interpolator calibration signal comprises:
generating a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal; and
adapting the phase interpolator calibration signal based on the digital phase error signal.

13. The method, as recited in claim 12 , further comprising:
generating a frequency-divided output clock signal in response to the output clock signal and an integer code; and
generating the timestamp signal, the timestamp signal including digital codes corresponding to edges of the frequency-divided output clock signal based on the clock signal.

14. The method, as recited in claim 12 , further comprising:
generating a divider control code and phase interpolator control code based on the control code; and
controlling a phase interpolator circuit based on a combination of the phase interpolator calibration signal and the phase interpolator control code.

15. The method, as recited in claim 12 , wherein the digital phase error signal has zero mean.

16. The method, as recited in claim 12 , further comprising:
generating the reference timestamp signal with the same period as the timestamp signal.

17. The method, as recited in claim 12 , further comprising:
generating an integer-divided output clock signal;
generating an integer-divided clock signal; and
generating the timestamp signal based on the integer-divided output clock signal and the integer-divided clock signal.

18. The method, as recited in claim 12 , further comprising:
selectively providing an active output clock signal generated by one of a plurality of output interpolative dividers;
generating a frequency-divided active clock signal in response to the active output clock signal and a corresponding integer code;
generating a corresponding timestamp signal based on edges of the frequency-divided active clock signal; and
periodically updating an active phase interpolator calibration signal based on the clock signal, the active output clock signal, and a corresponding phase interpolator code.

19. The method, as recited in claim 18 , wherein the selectively providing is round-robin selection of the active output clock signal from the plurality of output interpolative dividers.

20. A method comprising:
generating an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal;
generating a digital error signal based on a downsampled version of the output clock signal and an estimated version of the do

Assignees

• Silicon Lab Inc

Inventors

• Monk Timothy A
• Pastorello Douglas F

Classifications

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03H7/06

  including resistors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• H03L7/23

  with pulse counters or frequency dividers · CPC title