Memory device for changing pass voltage

Patent metadata

Field	Value
Publication number	US-11127472-B2
Application number	US-202016806535-A
Country	US
Kind code	B2
Filing date	Mar 2, 2020
Priority date	Jan 10, 2018
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

First claim

What is claimed is:

1. A memory device, comprising:
a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, wherein the selected word line and the unselected word lines are connected to a plurality of memory cells;
a dummy voltage supply unit that provides a dummy voltage to the selected word line before the read voltage is provided to the selected word line;
a degradation level detection circuit that detects a degradation level of memory cells connected to the selected word line based on data of memory cells that receive the dummy voltage, wherein the memory cells connected to the selected word line and the memory cells that receive the dummy voltage are included in the plurality of memory cells; and
a pass voltage change circuit that changes the pass voltage provided to the unselected word lines based on the degradation level.

2. The memory device of claim 1 , wherein the dummy voltage supply unit provides the dummy voltage a plurality of times before a read operation of each of a plurality of bit pages of a single page.

3. The memory device of claim 1 , wherein the dummy voltage supply unit provides the dummy voltage before a read operation of a single page.

4. The memory device of claim 1 , wherein the degradation level detection circuit determines a change of a threshold voltage of the memory cells that receive the dummy voltage by counting at least one of ON cells and OFF cells corresponding to the dummy voltage based on the data of the memory cells that receive the dummy voltage.

5. The memory device of claim 1 , wherein the degradation level detection circuit detects the degradation level based on a change of a threshold voltage of the memory cells that receive the dummy voltage.

6. The memory device of claim 4 , wherein the pass voltage change circuit reduces the pass voltage in response to the change of the threshold voltage.

7. The memory device of claim 1 , wherein the pass voltage change circuit provides the pass voltage having been changed in a time section in which the read voltage is applied.

8. A memory device, comprising:
a memory cell array comprising a plurality of memory cells connected to word lines and bit lines, wherein each of memory cells stores two or more bits of data;
a voltage generator that provides a read voltage to a selected word line of the word lines and provides a pass voltage to a plurality of unselected word lines of the word lines;
a pass voltage change circuit that changes the pass voltage provided to the unselected word lines based on a degradation level of memory cells,
wherein the voltage generator provides a first pass voltage to the unselected word lines during a first time period for reading a first bit of data stored in a selected memory cell connected to the selected word line, and provides a second pass voltage different from the first pass voltage to the unselected word lines during a second time period for reading a second bit of data stored in the selected memory cell.

9. The memory device of claim 8 , wherein the first bit is an upper bit and the second bit is a lower bit.

10. The memory device of claim 8 , wherein the first bit is aft a lower bit and the second bit is an upper bit.

11. The memory device of claim 8 , wherein the first pass voltage includes a prior pass voltage provided to the unselected word lines at a first time point of the first time period and a posterior pass voltage provided to the unselected word lines at a second time point after the first time point,
wherein the prior pass voltage and the posterior pass voltage have different magnitudes.

12. The memory device of claim 8 , wherein the first pass voltage is determined according to the degradation level detected from a dummy voltage provided prior to the read voltage,
wherein the second pass voltage is determined according to the degradation level detected from a read voltage during the first time period.

13. The memory device of claim 12 , wherein the voltage generator is configured to provide a third pass voltage varied according to the degradation level detected during the second time period to the unselected word lines during a third time period in which a third bit of the selected memory cell is read.

14. A memory device, comprising:
a memory cell array comprising a plurality of pages, wherein each of the pages comprises a plurality of memory cells; and
a pass voltage change circuit that changes a pass voltage supplied to pages connected to unselected word lines based on a degradation level of a threshold voltage of memory cells included in a page connected to a selected word line,
wherein the pages connected to the unselected word lines and the page connected to the selected word line are included in the plurality of pages,
wherein the pass voltage change circuit provides the pass voltage having been changed to at least one page from among the pages connected to the unselected word lines.

15. The memory device of claim 14 , wherein the pass voltage change circuit provides the pass voltage having been changed to at least one page in which a read operation is completed,
wherein the at least one page in which the read operation is completed is included in the pages connected to the unselected word lines.

16. The memory device of claim 15 , wherein the at least one page that receives the pass voltage having been changed is disposed on a side based on the selected word line.

17. The memory device of claim 16 , wherein the pass voltage is received by a plurality of pages, the pages that receive the pass voltage are sequentially disposed, and the read operation is performed in an arrangement direction of the sequentially disposed pages.

18. The memory device of claim 14 , wherein the pass voltage change circuit provides the pass voltage having been changed to all of the pages connected to the unselected word lines.

19. The memory device of claim 14 , wherein the pass voltage change circuit provides the pass voltage having been changed to pages disposed adjacent to the page connected to the selected word line, wherein the pages disposed adjacent to the page connected to the selected word line are included in the unselected word lines.

20. The memory device of claim 14 , wherein the degradation level is provided by a memory controller that communicates with the memory device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Han Jun
• Kim Seung Bum
• Park Il Han

Classifications

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/07

  Responding to the occurrence of a fault, e.g. fault tolerance · CPC title

• G11C29/50004

  of threshold voltage · CPC title