Method for creating through-connected vias and conductors on a substrate

US11107702B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11107702-B2
Application numberUS-202016924600-A
CountryUS
Kind codeB2
Filing dateJul 9, 2020
Priority dateApr 2, 2015
Publication dateAug 31, 2021
Grant dateAug 31, 2021

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor through the substrate, by forming structures in the planes of a substrate. These structures may include interconnect lines, bond pads, and other structures, and improve the performance of subsequent unique processing while simultaneously reducing the manufacturing complexity to reduce time and cost. These structures are formed by selective etching using chemical mechanical polishing, and then completed using a single fill step with a conductive material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for creating electrically or thermally conductive vias in a glass substrate, the method comprising the steps of: depositing a powder including copper particles on a first side of the glass substrate having holes so as to define a deposited powder in the holes; drying the deposited powder after the powder has been exposed to a non-polar solvent; and depositing the powder on a reverse side of the glass substrate and into the holes. 2. The method of claim 1 , wherein the copper particles are coated with silver. 3. The method of claim 1 , further comprising the steps of encapsulating the glass substrate in a polymer envelope and subjecting the polymer envelope to vacuum sealing to create a tight seal between the glass substrate and an inner layer of the polymer envelope. 4. The method of claim 3 , further comprising the step of subjecting the polymer envelope to an isostatic pressure. 5. The method of claim 4 , wherein the subjecting step further comprises the step of subjecting the polymer envelope to the isostatic pressure and a constant temperature to maximize via fill density and to cause particle-to-particle bonding or sintering of the copper particles. 6. The method of claim 5 , wherein the constant temperature is selected based at least on a material type of the copper particles and a via aspect ratio of the glass substrate. 7. The method of claim 6 , wherein the encapsulating step and the subjecting steps are performed after the first depositing step and prior to the second depositing step. 8. The method of claim 7 , further comprising performing the encapsulating step and the subjecting steps after the second depositing step. 9. The method of claim 1 , further comprising the step of depositing the powder into a trench formed in the glass substrate, and drying the powder in the trench. 10. The method of claim 9 , further comprising the steps of: encapsulating the glass substrate in a polymer envelope after the step of depositing the powder into the trench, and subsequently subjecting the polymer envelope to vacuum sealing to create a tight seal between the glass substrate and an inner layer of the polymer envelope; and after the encapsulating step, subjecting the polymer envelope to an isostatic pressure. 11. The method of claim 1 , further comprising the step of polishing the powder after the depositing steps. 12. The method of claim 1 , further comprising the step of polishing the powder into the holes. 13. The method of claim 1 , further comprising repeating the depositing steps. 14. The method of claim 1 , further comprising the step of sintering the powder. 15. The method of claim 1 , wherein the resulting thermally or electrically conductive vias are finished to be planar to a surface of the glass substrate. 16. The method of claim 1 , further comprising the step of applying rotational and vibratory forces to the glass substrate to achieve a desired fill density of the holes. 17. The method of claim 1 , wherein the drying step comprises applying a vacuum to the powder. 18. The method of claim 1 , wherein the holes include a through hole. 19. The method of claim 1 , wherein the holes include a blind hole. 20. The method of claim 1 , wherein the holes include a horizontal hole.

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What does patent US11107702B2 cover?
A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor through the substrate, by forming structures in the planes of a substrate. These structures may include interconnect lines, bond pads, and other structures, and improve the performance of subsequent unique processing while simultaneously redu…
Who is the assignee on this patent?
Samtec Inc
What technology area does this patent fall under?
Primary CPC classification H10W70/095. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 31 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).