Analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11088704-B2
Application number	US-202016896409-A
Country	US
Kind code	B2
Filing date	Jun 9, 2020
Priority date	Sep 9, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

An analog-to-digital converter (ADC) is provided. The ADC receives an analog input signal and generates a digital code. The ADC includes a sigma-delta modulator (SDM), a decimation filter and a detection circuit. The SDM includes a loop filter, a quantizer and a digital-to-analog converter (DAC). The loop filter receives the analog input signal. The quantizer is coupled to the loop filter and quantizes an output of the loop filter to generate a digital output signal. The DAC is coupled to the quantizer and the loop filter. The decimation filter is coupled to the SDM and converts the digital output signal into the digital code. The detection circuit is coupled to the SDM and detects a node voltage of the SDM and generate a control signal. The control signal is utilized to control the loop filter, the quantizer, a feedback path of the SDM and/or a feedforward path of the SDM.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) configured to receive an analog input signal and generate a digital code, comprising:
a sigma-delta modulator (SDM), comprising:
a loop filter configured to receive the analog input signal;
a quantizer, coupled to the loop filter and configured to quantize an output of the loop filter to generate a digital output signal; and
a digital-to-analog converter (DAC), coupled to the quantizer and the loop filter;
a decimation filter, coupled to the SDM and configured to convert the digital output signal to the digital code; and
a detection circuit, coupled to the SDM and configured to detect a node voltage of the SDM and generate a control signal;
wherein the control signal is utilized to control the loop filter and/or the quantizer.

2. The ADC of claim 1 , wherein the loop filter comprises a resonator, the resonator comprises an operational amplifier, and the control signal is utilized to turn off the operational amplifier.

3. The ADC of claim 1 , wherein the loop filter comprises a resonator, and the control signal is utilized to control the resonator to be inactive.

4. The ADC of claim 3 , wherein the resonator is a first resonator, the loop filter further comprises a second resonator, an input terminal of the second resonator is coupled to an output terminal of the first resonator, the SDM further comprises a switch coupled between the loop filter and the DAC, and the control signal is utilized to control the switch in such a way that when the first resonator is inactive, an output terminal of the DAC is coupled to the input terminal of the second resonator.

5. The ADC of claim 1 , wherein the loop filter comprises a first resonator and a second resonator, an input terminal of the second resonator is coupled to an output terminal of the first resonator, the SDM further comprises a switch coupled between the loop filter and the DAC, and the control signal is utilized to control the switch to accordingly control an output terminal of the DAC to be coupled to an input terminal of the first resonator or the input terminal of the second resonator.

6. The ADC of claim 1 , wherein the detection circuit comprises a low-resolution ADC, and the number of bits of the low-resolution ADC is less than the number of bits of the ADC.

7. The ADC of claim 1 , wherein the control signal is utilized to control a full swing range of an input signal to the quantizer.

8. The ADC of claim 1 , wherein the ADC further comprises a clamping circuit coupled to the SDM, and the control signal is utilized to control a clamping voltage of the clamping circuit.

9. An analog-to-digital converter (ADC) configured to receive an analog input signal and generate a digital code, comprising:
a sigma-delta modulator (SDM), comprising:
a loop filter configured to receive the analog input signal;
a quantizer, coupled to the loop filter and configured to quantize an output of the loop filter to generate a digital output signal; and
a digital-to-analog converter (DAC), coupled to the quantizer and the loop filter;
a decimation filter, coupled to the SDM and configured to convert the digital output signal to the digital code;
a detection circuit, coupled to the SDM and configured to detect a node voltage of the SDM and generate a detection result; and
a control circuit, coupled to the detection circuit and configured to generate a control signal according to the detection result;
wherein the control signal is utilized to control the loop filter and/or the quantizer.

10. The ADC of claim 9 , wherein the detection circuit is a low-resolution ADC, and the number of bits of the low-resolution ADC is less than the number of bits of the ADC.

11. The ADC of claim 9 , wherein the loop filter comprises a resonator, the resonator comprises an operational amplifier, and the control signal is utilized to turn off the operational amplifier.

12. The ADC of claim 9 , wherein the loop filter comprises a resonator, and the control signal is utilized to control the resonator to be inactive.

13. The ADC of claim 12 , wherein the resonator is a first resonator, the loop filter further comprises a second resonator, an input terminal of the second resonator is coupled to an output terminal of the first resonator, the SDM further comprises a switch coupled between the loop filter and the DAC, and the control signal is utilized to control the switch in such a way that when the first resonator is inactive, an output terminal of the DAC is coupled to the input terminal of the second resonator.

14. The ADC of claim 9 , wherein the loop filter comprises a first resonator and a second resonator, an input terminal of the second resonator is coupled to an output terminal of the first resonator, the SDM further comprises a switch coupled between the loop filter and the DAC, and the control signal is utilized to control the switch to accordingly control an output terminal of the DAC to be coupled to an input terminal of the first resonator or the input terminal of the second resonator.

15. The ADC of claim 9 , wherein the ADC further comprises a clamping circuit coupled to the SDM, and the control signal is utilized to control a clamping voltage of the clamping circuit.

16. The ADC of claim 9 , wherein the control signal is utilized to control a full swing range of an input signal to the quantizer.

Assignees

• Realtek Semiconductor Corp

Inventors

• Chen Chih-Lung
• Huang Shih-Hsiung

Classifications

• H03M3/426

  the quantiser being a successive approximation type analogue/digital converter · CPC title

• H03M3/444 Primary

  using non-linear elements, e.g. limiters · CPC title

• H03M3/494

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title