Correction method and correction circuit for sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-10778244-B2
Application number	US-201916519103-A
Country	US
Kind code	B2
Filing date	Jul 23, 2019
Priority date	Sep 27, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes the following steps: controlling the DAC not to receive the output of the quantizer; controlling the SDM to stop receiving signals; inputting a test signal to the DAC; converting the output of the loop filter to a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the result of comparing the digital signal and the preset value.

First claim

What is claimed is:

1. A correction method for correcting a sigma-delta modulator (SDM), the SDM comprising a loop filter, a quantizer, and a digital-to-analog converter (DAC), the correction method comprising:
controlling the DAC not to receive an output of the quantizer;
controlling the SDM to stop receiving signals;
inputting a test signal to the DAC;
using an analog-to-digital converter (ADC) to convert an output of the loop filter into a digital signal;
comparing the digital signal with a preset value; and
adjusting the loop filter according to a result of comparing the digital signal with the preset value.

2. The correction method of claim 1 , wherein the SDM further comprises an excess loop delay (ELD) compensation circuit, the correction method further comprising:
adjusting the ELD compensation circuit according to the result of comparing the digital signal with the preset value.

3. The correction method of claim 1 , wherein the step of adjusting the loop filter according to the result of comparing the digital signal with the preset value adjusts a parameter of the loop filter.

4. The correction method of claim 1 , wherein the ADC is not a component of the SDM.

5. A correction circuit for correcting a sigma-delta modulator (SDM), the SDM comprising a loop filter, a quantizer, and a digital-to-analog converter (DAC), the correction circuit comprising:
a memory storing a plurality of program instructions and a preset value;
a control circuit coupled to the memory and configured to execute the program instructions to correct the SDM; and
an analog-to-digital converter (ADC) coupled between the loop filter and the control circuit;
wherein a process of correcting the SDM comprises following steps:
controlling the DAC not to receive an output of the quantizer;
controlling the SDM to stop receiving signals;
inputting a test signal to the DAC;
the ADC converting an output of the loop filter into a digital signal;
comparing the digital signal with the preset value; and
adjusting the loop filter according to a result of comparing the digital signal with the preset value.

6. The correction circuit of claim 5 , wherein the SDM further comprises an excess loop delay (ELD) compensation circuit, and the process of correcting the SDM further comprises:
adjusting the ELD compensation circuit according to the result of comparing the digital signal with the preset value.

7. The correction circuit of claim 5 , wherein the step of adjusting the loop filter according to the result of comparing the digital signal with the preset value adjusts a parameter of the loop filter.

8. The correction circuit of claim 5 , wherein the ADC is not a component of the SDM.

Assignees

• Realtek Semiconductor Corp

Inventors

• Chen Chih-Lung
• Lai Jie-Fan
• Chen Yu-Chang
• Huang Shih-Hsiung

Classifications

• H03M3/352

  of deviations from the desired transfer characteristic · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/378 Primary

  Testing · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title