Sigma delta modulator, integrated circuit and method therefor

Patent metadata

Field	Value
Publication number	US-10439634-B2
Application number	US-201815935045-A
Country	US
Kind code	B2
Filing date	Mar 25, 2018
Priority date	Jun 8, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

First claim

The invention claimed is:

1. A multi-bit continuous-time sigma-delta modulator, SDM, comprising:
an input configured to receive an input analog signal;
a first summing junction ( 304 ) configured to subtract a feedback analog signalfrom the input analog signal;
a loop filter configured to filter an output signal from the first summing junction:
an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and
a feedback path for routing the digital output signal to the first summing junction, wherein the feedback path comprises a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form; wherein the multi-bit SDM is characterised in that the ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches configured to function in a complementary manner and provide a combined complementary output.

2. The multi-bit continuous-time SDM of claim 1 , wherein the pair of latches are configured to provide a complementary output that comprises alternate latches of the pair being inactivated or activated in an out-of-synchronisation manner.

3. The multi-bit continuous-time SDM of claim 1 , wherein the complementary arrangement between the paired latches comprises a first latch of the pair of latches being configured to be in a regeneration mode concurrently with a second latch of the pair of latches being configured to be in a reset mode and acquiring a next initial condition.

4. The multi-bit continuous-time SDM of claim 3 , wherein the complementary arrangement between the pair of latches provides a first ADC sampling period for regeneration and a second ADC Ts for a reset operation and to take the next initial condition.

5. The multi-bit continuous-time SDM of claim 4 , wherein the reset operation and taking the next initial condition happens in series.

6. The multi-bit continuous-time SDM of claim 4 , wherein the reset operation and taking the next initial condition happens in parallel.

7. The multi-bit continuous-time SDM of claim 1 , wherein the multi-bit SDM is further characterised in that the ADC comprises multiple per-bit parallel loops comprising a plurality of paths, each path comprising a pair of latches coupled to an output of a current summing junction and configured to provide a one-bit contribution to the digital output signal.

8. The multi-bit continuous-time SDM of claim 7 , wherein the multi-bit SDM is characterised in that the ADC multiple per-bit parallel loops comprise a plurality of paths, each path comprising:
a voltage-to-current converter configured to receive the filtered analog output signal in voltage domain and convert the filtered analog output signal into a current domain;
a DAC configured to selectively convert one bit of the multi-bit quantization digital output signal to an analog form; and
a current summing junction configured to sum a current domain representation of the filtered analog output signal, a current domain representation of the multi-bit quantization digital output signal from the DAC; and a dedicated reference current for each path.

9. The multi-bit continuous-time SDM of claim 8 , wherein the DAC in each loop comprises an excess loop delay, ELD, DAC configured to selectively convert one bit of the digital output signal to an analog form.

10. The multi-bit continuous-time SDM of claim 1 , wherein the plurality of paths is a plurality of quantizer paths with each path comprising a transconductance amplifier.

11. The multi-bit continuous-time SDM of claim 1 , wherein the plurality of N-bit comparator latches comprise a plurality of 1-bit comparator latches.

12. The multi-bit continuous-time SDM of claim 1 , wherein the multi-bit continuous-time SDM is formed across a plurality of slices comprising a 1-bit ADC, such that a reference current circuit provides the same common-mode current across different slices and where only the differential current is different across different slices.

13. An integrated circuit comprising a multi-bit continuous-time sigma-delta modulator, SDM, comprising:
an input configured to receive an input analog signal;
a first summing junction configured to subtract a feedback analog signalfrom the input analog signal;
a loop filter configured to filter an output signal from the first summing junction:
an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and
a feedback path for routing the digital output signal to the first summing junction, wherein the feedback path comprises a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form; wherein the multi-bit SDM is characterised in that the ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches configured to function in a complementary manner and provide a combined complementary output.

14. A method for generating a multi-bit quantization digital output signal by a multi-bit continuous-time sigma-delta modulator, SDM, the method comprising:
receiving an input analog signal;
subtracting a feedback analog signal from the input analog signal in a first summing junction;
filtering an output signal from the first summing junction:
converting the filtered analog output signal to a digital output signalin an analog-to-digital converter, ADC;
feeding back the digital output signal to the first summing junction, via a digital-to-analog converter, DAC, converting the digital output signal to an analog form;
wherein the method is characterised by:
operating a plurality of N-bit paired latches in a complementary manner; and
providing a combined complementary output from the plurality of paired latches.

15. The method of claim 14 , further comprising:
inactivating or activating in an out-of-synchronisation manner respective latches from the paired latches; and
providing a complementary output from the plurality of paired latches by alternately coupling the respective latches to an output of the SDM.

Assignees

• Nxp Bv

Inventors

• Bolatkale Muhammed
• Breems Lucien Johannes

Classifications

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M3/42

  having multiple quantisers arranged in parallel loops · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/322 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M3/378) · CPC title