Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Patent metadata

Field	Value
Publication number	US-11087841-B2
Application number	US-202016784332-A
Country	US
Kind code	B2
Filing date	Feb 7, 2020
Priority date	Jun 10, 2011
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a substrate;
a logic layer disposed on the substrate, the logic layer comprising a pass gate transistor and a gain stage transistor;
a first layer comprising a plurality of local bit lines (LBLs), wherein at least one of the plurality of LBLs is coupled to the gain stage transistor;
a second layer comprising a plurality of word lines (WLs); and
a memory layer comprising a plurality of memory elements, each being re-writable, non-volatile, and having two terminals, wherein each of the plurality of memory elements is positioned between a cross-point of one of the plurality of WLs with one of the plurality of LBLs and is electrically coupled in series with its respective WL and LBL.

2. The non-volatile memory device of claim 1 , further comprising a third layer comprising a plurality of global bit lines (GBLs), wherein at least one of the plurality of GBLs is coupled to the pass gate transistor and the gain stage transistor in the logic layer.

3. The non-volatile memory device of claim 1 , further comprising:
a sense amplifier;
a decoder circuit coupled to a gate of the pass gate transistor; and
a third layer comprising a plurality of global bit lines (GBLs), wherein a first GBL of the plurality of GBLs is coupled to a drain of the pass gate transistor, a drain of the gain stage transistor, and the sense amplifier, wherein a first LBL of the plurality of LBLs is coupled to a source of the pass gate transistor, and wherein the first LBL is coupled to gain stage transistor through the pass gate transistor.

4. The non-volatile memory device of claim 1 , further comprising:
a decoder circuit coupled to a gate of the pass gate transistor; and
a third layer comprising a plurality of global bit lines (GBLs), wherein a first GBL of the plurality of GBLs is coupled to a drain of the pass gate transistor, wherein a first LBL of the plurality of LBLs is coupled to a source of the pass gate transistor, and wherein the first LBL is coupled to gain stage transistor through the pass gate transistor.

5. The non-volatile memory device of claim 1 , further comprising:
a third layer comprising a second plurality of LBLs; and
a second memory layer comprising a second plurality of memory elements.

6. The non-volatile memory device of claim 1 , further comprising:
a front-end-of-the-line (FEOL) circuitry portion comprising the substrate and the logic layer; and
a back-end-of-the-line (BEOL) circuitry portion comprising the first layer, the second layer, and the memory layer.

7. The non-volatile memory device of claim 6 , wherein the FEOL circuitry portion further comprises a third layer comprising a plurality of global bit lines (GBLs).

8. The non-volatile memory device of claim 6 , wherein the BEOL circuitry portion further comprises one or more additional memory layers.

9. The non-volatile memory device of claim 1 , wherein the plurality of WLs are organized as a plurality of WL groups, each WL group of the plurality of WL groups comprising two or more of the plurality of WLs.

10. The non-volatile memory device of claim 1 , further comprising a metallization layer comprising a metal trace, wherein the metal trace is coupled to a source of the pass gate transistor via a first interconnect coupled between the metallization layer and the logic layer, wherein the metal trace is coupled to a gate of the gain stage transistor via a second interconnect coupled between the metallization layer and the logic layer.

11. The non-volatile memory device of claim 10 , wherein the metal trace is coupled to a first LBL of the plurality of LBLs via a third interconnect coupled between the metallization layer and the first layer.

12. An apparatus comprising:
a memory array of a plurality of non-volatile memory devices, the memory array comprising:
a plurality of local bit line (LBL) layers, each layer comprising a plurality of LBLs;
a plurality of word line (WL) layers, each layer comprising a WL; and
a plurality of memory layers of memory elements, each memory element being re-writable, non-volatile, having two terminals, being positioned between a cross-point of a WL of the plurality of WL layers with a LBL of one of the plurality of LBL layers and electrically coupled in series with the WL and LBL; and

active circuitry coupled to the memory array, wherein active circuitry comprises:
a substrate;
a logic layer disposed on the substrate, the logic layer comprising a plurality of pass gate transistors and a plurality of gain stage transistors; and
a global bit line (GBL) layer comprising a plurality of GBLs, wherein at least one of the plurality of GBLs is coupled to one of the plurality of pass gate transistors and one of the plurality of gain stage transistors in the logic layer.

13. The apparatus of claim 12 , wherein:
a first memory element of the plurality of memory layers of memory elements is positioned between a first cross-point of a first WL of the plurality of WL layers with a first LBL of one of the plurality of LBL layers;
the first LBL is coupled to a first pass gate transistor of the plurality of pass gate transistors; and
a first GBL of the plurality of GBLs is coupled to the first pass gate transistor.

14. The apparatus of claim 13 , wherein:
the first LBL is coupled to a first gain stage transistor of the plurality of gain stage transistors through the first pass gate transistor; and
the first GBL of the plurality of GBLs is coupled to the first gain stage transistor.

15. The apparatus of claim 14 , further comprising:
a sense amplifier coupled to the first pass gate transistor and the first gain stage transistor; and
a decoder circuit coupled to a gate of the first pass gate transistor.

16. A non-volatile memory comprising:
a first layer of a plurality of global bit lines (GBLs);
a stack of layers comprising a cross-point memory array, the cross-point memory array comprising a plurality of word lines (WLs) in one or more second layers, a plurality of memory array portions in one or more third layers, and a plurality of local bit lines (LBLs) in one or more fourth layers, each memory array portion being selectively electrically coupled with one of the plurality of GBLs, and each memory array portion including:
a local bit line (LBL) of the plurality of LBLs; and
a re-writable non-volatile two-terminal memory element positioned between a cross-point of the LBL and a word line (WL) of the plurality of WLs and configured to store at least one bit of data; and

a fifth layer comprising logic circuitry configured to perform data operations on one or more of the plurality of memory array portions of the cross-point memory array.

17. The non-volatile memory of claim 16 , further comprising an amplifier electrically coupled with the LBL and a corresponding GBL, the amplifier to produce an amplified signal on or along the corresponding GBL.

18. The non-volatile memory of claim 17 , wherein during a read operation the amplifier is configured to produce the amplified signal on or along the corresponding GBL with a magnitude that is dependent upon a memory state of a selected re-writable non-volatile two-terminal memory element.

19. The non-volatile memory of claim 17 , wherein during a read operation the amplifier is configured to produce the amplified signal on or along the corresponding GBL with a magnitude that is dependent upon a resistive state of a selected re-writable non-volatile two-terminal memory element.

20. The non-volatile m

Assignees

• Unity Semiconductor Corp

Inventors

• Siau Chang Hua
• Bateman Bruce Lynn

Classifications

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C7/18 Primary

  Bit line organisation; Bit line lay-out · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title