Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Patent metadata

Field	Value
Publication number	US-9870823-B2
Application number	US-201715596499-A
Country	US
Kind code	B2
Filing date	May 16, 2017
Priority date	Jun 10, 2011
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a first wordline (WL);
a first local bitline (LBL);
a first global bitline (GBL);
a first re-writable non-volatile two-terminal memory element positioned between the first WL and the first LBL;
a first transistor with a first terminal coupled to the first LBL and a second terminal coupled to the first GBL; and
a second transistor with a gate coupled to the first LBL and a first terminal coupled to the first GBL.

2. The non-volatile memory device of claim 1 , further comprising:
a second WL; and
a second re-writable non-volatile two-terminal memory element positioned between the second WL and the first LBL.

3. The non-volatile memory device of claim 1 , further comprising:
a second LBL;
a second GBL;
a second re-writable non-volatile two-terminal memory element positioned between the first WL and the second LBL;
a third transistor with a first terminal coupled to the second LBL and a second terminal coupled to the second GBL; and
a fourth transistor with a gate coupled to the second LBL and a first terminal coupled to the second GBL.

4. The non-volatile memory device of claim 1 , wherein the first transistor is a pass gate transistor with a gate coupled to receive a pass gate signal, and wherein the second transistor is a common source amplifier.

5. The non-volatile memory device of claim 4 , wherein the common source amplifier is to isolate a capacitance of the first LBL from a capacitance of the first GBL.

6. The non-volatile memory device of claim 4 , wherein the common source amplifier is to amplify a signal on the first LBL to obtain an amplified signal on the first GBL during a read operation, the amplified signal being representative of a stored memory state of the first re-writable non-volatile two-terminal memory element.

Assignees

• Unity Semiconductor Corp

Inventors

• Siau Chang Hua
• Bateman Bruce Lynn

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title