Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Patent metadata

Field	Value
Publication number	US-9691480-B2
Application number	US-201615205882-A
Country	US
Kind code	B2
Filing date	Jul 8, 2016
Priority date	Jun 10, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

First claim

What is claimed is:

1. A method of operating a non-volatile memory array, comprising:
selecting one of a plurality of re-writable non-volatile two-terminal memory elements of the non-volatile memory array;
during a write operation of the selected memory element, electrically coupling a local bitline (LBL), of a plurality of local bitlines (LBLs), associated with the selected memory element with an associated global bit line (GBL) of a plurality of global bit lines (GBLs); and
during a read operation of the selected memory element:
activating a switch device associated with the LBL; and
applying a read voltage across the selected memory element.

2. The method of claim 1 , wherein the write operation is a program operation.

3. The method of claim 2 , wherein the read operation is performed to determine that the selected memory element has been programed to a desired high-resistance state.

4. The method of claim 3 , further comprising repeating the programming operation in response to a determination that the selected memory element has not been fully programmed and repeating the read operation to determine that the selected memory element has been programed to the desired high-resistance state.

5. The method of claim 2 , wherein the write operation to the memory elements does not require a prior erase operation.

6. The method of claim 1 , wherein the write operation is an erase operation.

7. The method of claim 6 , wherein the read operation is performed to determine that the selected memory element has been erased to a desired low-resistance state.

8. The method of claim 7 , further comprising repeating the erase operation in response to a determination that the selected memory element has not been fully erased and repeating the read operation to determine that the selected memory element has been erased to the desired low-resistance state.

9. The method of claim 1 , further comprising:
charging a capacitance of the LBL to a local bit line voltage; and
amplifying and conducting the local bit line voltage to generate an amplified local bit line voltage.

10. The method of claim 9 , further comprising conducting the amplified local bit line voltage along the GBL.

11. The method of claim 9 , wherein a magnitude of the amplified local bit line voltage is dependent upon a memory state of the memory element.

12. The method of claim 9 , wherein a magnitude of the amplified local bit line voltage is dependent upon a resistive state of the selected memory element.

13. The method of claim 9 , wherein the amplified local bit line voltage is dependent upon a memory state of a selected memory element.

14. The method of claim 9 , wherein a magnitude of the amplified local bit line voltage is dependent upon a resistive state of memory element.

15. The method of claim 1 , wherein activating the switch device selectively electrically couples the LBL with the associated GBL.

16. The method of claim 1 , wherein activating the switch device is performed during times when the selected memory element associated with the LBL is being programmed or erased.

17. The method of claim 16 , activating the switch device is configured to isolate the LBL from the associated GBL during times when the selected memory element is being read.

18. The method of claim 1 , wherein the memory element is configurable to two or more resistive states.

19. The method of claim 1 , wherein selecting the one of a plurality of re-writable non-volatile two-terminal memory elements of the non-volatile memory array comprises individually address the one of a plurality of re-writable non-volatile two-terminal memory elements for data operations on a basis of at least a single bit.

Assignees

• Unity Semiconductor Corp

Inventors

• Siau Chang Hua
• Bateman Bruce Lynn

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C5/08

  for interconnecting magnetic elements, e.g. toroidal cores · CPC title